01-31-2013 08:05 AM
After installing ISE Webpack 14.4 and open an example project based on schematics, I tried to synthesize a CORE Generator IP, but a prompt message appears:
There is no project open.
You may browse the IP Catalog but you will not be able to generate any cores until you open or create a project.
All the libraries of CORE IP´s appears “grayed out”, meaning that they are not available.
I tried opening several example projects, but the problem remains unsolved.
I have been programming Xilinx chips since some 24 years, all families.
Thank you for any idea
01-31-2013 12:11 PM
This is a bit confusing. Core generator has its own project files, which are not the same as
the ISE project. Normally if you use the ISE GUI and start Core generator using the
Project --> New Source... dialog, it will create a core generator project for you. Otherwise
you can create a new project from within core generator, but then you should make sure
that the device settings are the same as for the ISE project that the cores will be used in.
02-01-2013 09:09 AM - edited 02-01-2013 09:14 AM
There is one known issue with the ISE 14.4 webpack install. When ever you try to create an IP core, all of the cores in the new source wizard will appear to be greyed out. Are you referring to this?
As a workaround for this you can use a full install of ISE 14.4.
If you want to work with the webpack install, then set the environmental variable XIL_CG_LOAD_ALL_FAMILIES=true and re-open the ISE/Coregen and try to create an IP core.
02-06-2013 04:04 AM
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
02-20-2013 11:20 AM
I have installed 14.4 ISE version and I cannot select IP core (I would like a single DCM). All Ips are grey inside the core generator and architecture wizard.
Please, can you explain the way to solve this problem?
02-21-2013 06:24 AM - edited 02-21-2013 06:24 AM
You can set the environmental variable XIL_CG_LOAD_ALL_FAMILIES=true and re-open the ISE/Coregen and try to create an IP core as mentioned in the earlier post.
Refer to http://www.xilinx.com/support/answers/11630.htm for details on how to set the env variables.
Else you can dowload the ISE 14.4 product update from http://www.xilinx.com/support/download/index.htm