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First Look: Rosetta on Virtex-6 and Spartan-6 FPGA

by Xilinx Employee on ‎09-07-2010 05:02 PM

In White Paper 286, I described the Rosetta program to design and test for soft errors. The program consists of predictions before we produce a product, neutron testing after the first parts come back, atmospheric arrays of 100 parts each, and underground arrays of 100 parts each (for alpha upsets), which accumulate data for a number of years after the product introduction.

 

We have already published the very first atmospheric results of our soft error rate testing program for the 40 and 45 nanometer Virtex-6 and Spartan-6 FPGA devices. See User Guide 116.

 

LANSCE

 

Los Alamos Neutron Science Center (LANSCE) is the gold standard used by the industry to get a quick measure of the soft error sensitivity from neutrons in the atmosphere. Virtex-6 and Spartan-6 FPGA results were measured in September of 2009. Converting the neutron flux at LANSCE to the JEDEC89A standard reference at New York City, we get: 95% confidence interval is +/- 20%

 

Virtex-6 FPGA

Configuration                       163 FIT/Mb

BRAM (no ECC)      147 FIT/Mb

 

Spartan-6 FPGA

Configuration                       129 FIT/Mb

BRAM (no ECC)      184 FIT/Mb

 

95% confidence interval implies that there is a 95% probability that the result lies within the interval specified, or that there is a 5% probability that the result is larger or smaller than what is noted.

 

Alpha Upsets from Packaging

 

In a previous blog (Package-Generated-Alpha-Particles), I described how the residual alpha emitting isotopes are a factor at the 45/40 nm node which must be accounted for.  As is stated in the blog, we keep improving resistance to atmospheric neutron upsets with each technology node, but the level of isotope contamination remains fixed, so now the alpha upsets are a factor.

 

If we take the predicted alpha upset rate and add that to the LANSCE results, we get:

 

Virtex-6 FPGA

Configuration                       243 FIT/Mb

BRAM (no ECC)      247 FIT/Mb

 

Spartan-6 FPGA

Configuration                       264 FIT/Mb

BRAM (no ECC)      644 FIT/Mb

 

The uncertainty in the above numbers is now much greater than before, as the estimates of the alpha contribution are no better than +100%/-50% (the alpha upsets could be double or half of what is stated in ug116.pdf). Combined with the +/-20% from the LANSCE tests, the total uncertainty will be the sum of all uncertainties.

 

Rosetta Arrays

 

We build arrays of 100 devices each and test them at various locations (as described in wp286.pdf above) as part of our product qualification process.

 

Rosetta testing includes the upsets from the atmospheric neutrons and the upsets from residual alpha emitting materials in the packaging (after all, the Rosetta results are “real life”).

 

At first glance, the Rosetta numbers look upsetting (pun intended), but that is often the case when you have so few upsets and so little time. The initial numbers from Rosetta always start out with large confidence interval extremes (the ‘from’ and ‘to’ numbers or +/- percent), and then come down to more reasonable numbers with more upsets over time. In fact, since August 10, 2010 (the release date of this report), we are now at:

 

Virtex-6 FPGA

Configuration                       163 FIT/Mb, from 66 to 377 (95% confidence interval)

BRAM (no ECC)      440 FIT/Mb, from 161 to 958 (95% confidence interval)

 

Spartan-6 FPGA

Configuration                       217 FIT/Mb, from 124 to 353 (95% confidence interval)

BRAM (no ECC)        68 FIT/Mb, from   2 to 381 (95% confidence interval)

 

In the coming quarters, it is expected that the Rosetta data will converge on the values customers will experience in their use of these products. The key to recognizing the usefulness of the numbers is to examine the confidence interval:  smaller is more confidence that the average shown is likely to be the right value.

About the Author
  • Austin graduated from UC Berkeley in 1974 and 1975 with his BS EECS in Electromagnetic (E&M) Theory and MS EECS in Communications and Information Theory. He worked in the telecommunications field for 20 years designing optical, microwave, and copper-based transmission systems. Austin joined the IC Design department for the Virtex product line at Xilinx in 1998. His role for the last four years is working for Xilinx Research Labs, where he is looking beyond the present technology issues. Austin has 69 patents.