Hello,
I'm trying to simulate a circuit in verilog with ISIM.
Some standard cells are defined in a way similar to the following:
`timescale 1ns / 10ps
`delay_mode_path
module myBuf (Z, A);
input A;
output Z;
buf #1 U1 (Z, A) ;
specify
(A +=> Z) = (1.1,0.1);
endspecify
endmodule
The problem I have is that the propagation delay relative to the rising edge is interpreted correctly (1.1 ns), while the falling edge is not (1 ns instead of 0.1 ns).
It seems like the simulator is not able to simulate propagation delays shorter than the reference time unit. But this should not happen, right?
(at least, if I write "buf #0.1 U1 (Z, A) ;" things work; but I have to import files with several definitions and I cannot change them all by hand)
Is it an ISIM bug?
Thank you in advance for your time.
Leonardo
