Synthesis

[cgauer]

I'm currently working on a system that incorporates a number of kcpsm6 units, which I want to be able to partially reconfigure.  Each PicoBlaze is housed inside a wrapper component that holds both it and its program ROM.  Before synthesizing my system, I placed a "keep hierarchy" constraint in this wrapper component so that it would remain distinct, and I could designate it as a reconfigurable partition.  When I try to build my system in PlanAhead, I get a Pack:2811 error for each PicoBlaze tile.  If I build a non-reconfigurable version of the system without applying the "keep hierarchy" constraints, everything works just fine.  I've used "keep hierarchy" in this fashion on self-written components before, but never on a picoblaze.  How could I solve this?  The complete error message is below, and I've attached the code for my wrapper component.

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints
   (BLKNM=pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico
   _proc/KCPSM6_SANDR) which requires the combination of the symbols listed
   below to be packed into a single SLICE component.

   The directed pack was not possible because: The top reasons for failure were:
       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[0].low_hwbuild.shift_rotate_flop".
       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[1].low_hwbuild.shift_rotate_flop".
       -> Function generator
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/d
   ata_path_loop[4].mid_shift_rotate.shift_rotate_lut/LUT6 is the LUT6 portion
   of the LUT6_2 and can only go into a LUT6 site.

       -> Function generator
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/d
   ata_path_loop[6].msb_shift_rotate.shift_rotate_lut/LUT6 is the LUT6 portion
   of the LUT6_2 and can only go into a LUT6 site.

       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[2].low_hwbuild.shift_rotate_flop".
       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[3].low_hwbuild.shift_rotate_flop".
       -> Function generator
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/d
   ata_path_loop[2].mid_shift_rotate.shift_rotate_lut/LUT6 is the LUT6 portion
   of the LUT6_2 and can only go into a LUT6 site.

       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[4].low_hwbuild.shift_rotate_flop".
       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[5].low_hwbuild.shift_rotate_flop".
       -> A legal placement was never found for register symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[6].low_hwbuild.shift_rotate_flop".

   The symbols involved are:
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[0].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[0])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[2].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[2])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[4].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[4])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[6].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[6])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[6].msb_shift_rotate.shift_rotate_lut/LUT5" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[6])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[4].mid_shift_rotate.shift_rotate_lut/LUT5" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[4])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[2].mid_shift_rotate.shift_rotate_lut/LUT5" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[2])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[0].lsb_shift_rotate.shift_rotate_lut/LUT5" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[0])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[6].msb_shift_rotate.shift_rotate_lut/LUT6" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[7])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[4].mid_shift_rotate.shift_rotate_lut/LUT6" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[5])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[2].mid_shift_rotate.shift_rotate_lut/LUT6" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[3])
       LUT symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[0].lsb_shift_rotate.shift_rotate_lut/LUT6" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_value[1])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[1].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[1])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[3].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[3])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[5].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[5])
       FLOP symbol
   "pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/
   data_path_loop[7].low_hwbuild.shift_rotate_flop" (Output Signal =
   pico_tile_tmr_unit_0/pico_tile_tmr_unit_0/USER_LOGIC_I/unit/proc1/pico_proc/s
   hift_rotate_result[7

[cgauer]

Note: this error is not limited to PlanAhead, and it occurs whether I floorplan the design or not.  If I try to synthesize my project in EDK with the keep hierarchy constraint active, I get the same error.

[cgauer]

Update:  I can get my design to build in XPS if I set "keep hierarchy" to "soft" instead of "true."  However, this does not help once I export the netlists to PlanAhead.  I have discovered that all is well as long as only one of my reconfigurable partitions contains a PicoBlaze; however, if I attempt to create multiple PicoBlaze components in separate partitions, I get the same Pack error.  I even tried synthesizing my system netlists with all of the PicoBlaze tiles as black boxes, synthesizing the PicoBlaze tile netlist in a separate project (with the "keep hierarchy" constraint removed), and using that to create the reconfigurable modules in PlanAhead; same problem.

[cgauer · Accepted solution]

I found the problem (after much struggling)!  It is probably analogous to this issue:

http://www.xilinx.com/support/answers/30705.htm

In my case, though, the offending constraint appears to be "hblknm" instead of "hlutnm."  To solve the problem, I had to modify the "generate data_path_loop" section of kcpsm6.vhd.  For each PicoBlaze partition in my design, I had to generate a new netlist from a version of kcpsm6.vhd which used a unique name for this code block, instead of "data_path_loop."  So the netlists are generated from files that contain data_path_loop00, data_path_loop01, etc.

[radisson_knowres]

Facing same issue, today, 3rd day of investigation, I finally found this thread which solved  it.

But I'm wondering, is this really THE solution, editing something that rather is a black box to us?

Any information from the Xilinx/Picoblaze experts?

Best regards,

Mark Radisson

[rcingham]

"Any information from the Xilinx/Picoblaze experts?"

Probably not in this forum, maybe in:
http://forums.xilinx.com/t5/PicoBlaze/bd-p/PicoBlaze