11-24-2009 06:20 AM - edited 11-24-2009 06:40 AM
I have an ADS6442 analog/digital converter with DDR input to the FPGA and the following data sheet values for my sampling rate (60 MHz):
t_Setup: Minimum 800ps; Typical 1100ps
t_Hold: Minimum 800ps; Typical 1100ps
Bit clock cycle-cycle jitter: 350ps pp
Data clock is 3.5*60 = 210 MHz, which gives me a clock period of 4.762ns.
From that information I created the following UCF location and timing constraints:
NET dataclk1_in_p LOC=L19 | IOSTANDARD=LVDS_25 | TNM_NET = dataclk1;
NET dataclk1_in_n LOC=K19 | IOSTANDARD=LVDS_25;
TIMESPEC TS_dataclk1 = PERIOD dataclk1 210 Mhz HIGH 50%;
NET adc1/dataclk_0 TNM = dataclk1_CLK0;
TIMEGRP dataclk1_CLK0_GRP = RISING dataclk1_CLK0;
TIMEGRP dataclk1_CLK180_GRP = FALLING dataclk1_CLK0;
# Minimum setup and hold times
OFFSET = IN 800ps VALID 1600ps BEFORE dataclk1_in_p TIMEGRP dataclk1_CLK0_GRP;
OFFSET = IN -1581ps VALID 1600ps BEFORE dataclk1_in_p TIMEGRP dataclk1_CLK180_GRP;
# Typical setup and hold times
#OFFSET = IN 1100ps VALID 1900ps BEFORE dataclk1_in_p TIMEGRP dataclk1_CLK0_GRP;
#OFFSET = IN -1281ps VALID 1900ps BEFORE dataclk1_in_p TIMEGRP dataclk1_CLK180_GRP;
Is that correct for the given data sheet values? My problem is that I have no problem adjusting the DCM PHASE_SHIFT value to meet "minimum" timing on a V5SX50T-1. But after switching to V5SX95T-2, I get timing errors in the range of 50ps per data line after re-adjusting PHASE_SHIFT to a slightly higher value. "Typical" timing however is achieved for both FPGA. Obviously the hold time of 1600ps is too low to achieve timing at any PHASE_SHIFT value. Is it wrong to add both "minimum"setup and hold times to calculate the minimum VALID time?
Thanks in advance
Solved! Go to Solution.
11-24-2009 07:37 AM
In answer to you last question. Refer to figure 2-2 of UG-612 (v11.1.1) it shows VALID to be what I would call hold time. In your case 800ps. What are you doing to compensate for trace delay?
I don't understant the 210MHz clock for a 60MHz sampling rate.
11-24-2009 07:50 AM
Hallo, thanks for answering.
Setup (t_su) and hold times (t_h) in the ADC datasheet are defined as shown in the attached picture.
In my understanding, VALID describes the total duration that the bit is valid. According to the picture this would be t_su + t_h.
The bit clock and data traces are the same length.The bit clock is fed into a DCM that uses fixed PHASE_SHIFT to compensate for the t_su and t_h values.
The sampling rate is 60 MSPS. The ADS6442 outputs the 14bit wide data on two LVDS pairs with DDR. So the bit clock is 60*14/2/2 = 210 MHz. This is all correct and tested with actual hardware.
11-24-2009 10:39 AM
I assume your using one of these boards ?
do TI provide such info as how to set up UCF file ?
Is Xapp 866 any use ?
or Xapp 774
both seem to deal with a similar ADC, and have design files enclosed.
You have two sets of constraints to make.
one is on the clock input, which is solly to do withthe clock speed.
the second is to do solely with the data inputs,
what is your FPGA device ?
how long is the data valid before the clock edge ?
Is rising and falling edge timing symetrical ?
how long is the data valid for ?
11-24-2009 10:55 AM
I'll take second go at that answer, having re read your initial posting, I think I have the answers needed.
One comment, things change with different ISE's
this is for ISE 11.3
I seporate the pin naming and IO standard assignments from the tiing constraints.
I dont' know why, but I always have done.
so just looking at the timing constraints.
# first set up the clock
NET "dataclk1_in_p" TNM_NET = dataclk1_in_p;
TIMESPEC TS_dataclk1_in_p = PERIOD "dataclk1_in_p" 4.762 ns HIGH 50%;
# now set up the data inputs with data timing
# data present for 1.6ns, centered around clock ( 0.8 ns before, 0.8 ns after )
# this needs to be for your data , which I am assume is called adc_data_h and adc_data_l
NET "adc_data_h" OFFSET = IN 0.8 ns VALID 1.6 ns BEFORE "dataclk1_in_p" RISING;
NET "adc_data_h" OFFSET = IN 0.8 ns VALID 1.6 ns BEFORE "dataclk1_in_p" FALLING;
NET "adc_data_l" OFFSET = IN 0.8 ns VALID 1.6 ns BEFORE "dataclk1_in_p" RISING;
NET "adc_data_l" OFFSET = IN 0.8 ns VALID 1.6 ns BEFORE "dataclk1_in_p" FALLING;
11-25-2009 07:35 AM
thank you for the answer. If I am correct, your timing constraints and mine match, except for the way to write them down. I tried yours, just to be sure, and got the same results. So I guess in the bigger SX95T my signals need more time to travel to their destination than in the SX50T. The higher speed grade does not compensate for this effect completely.
Thanks for clearity!
11-25-2009 08:56 AM
Are you using the IOSERDES ?
you need to instantiate it, but that will more than happily capture data at the 200 MHz clock rate,
I have had a V5 running at more than 300 MHz using the IOSERDES and it meets timing.
Is the data source synchronous at the FPGA ?
11-25-2009 09:04 AM
for faster designs I used ISERDES in the past. But I considered this design as "not that fast" and back in the days I designed it, I was not familiar with ISERDES yet. I think I will follow your advise and redesign the receiver block.
11-26-2009 09:17 AM
just had one other thought whilst I was workign on another design.
In your initial desing, are the IO regtisters in the IOB ?
I just had a design that sholuld have worked as well, but the code has 'evolved' over time, meaning the first register in this design could not be implimented in the IOB, so ISE puished it inside the FPGA, and it failed timming.
Took a while to find,
I noted that there is a new ( ish ) option to add a IOB=FORCE attribute in the HDL , which generates an error if the register is not able to be put in the IOB.
11-27-2009 04:14 AM
The IO registers are still in the IOB. But thanks for the advice, I didn't check that.
Right now I don't have time for the implementation of ISERDES. I will do that later and report on the success. But I'm sure this will solve the problem.