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Visitor
dayueili
Posts: 18
Registered: ‎10-17-2007
0

Verilog code for a pseudo random sequence generator

Could anyone post a Verilog code of a pseudo random sequence generator with 16-bit parallel output?
Expert Contributor
gszakacs
Posts: 7,152
Registered: ‎08-14-2007
0

Re: Verilog code for a pseudo random sequence generator

Check out:

http://www.easics.be/webtools/crctool

This is a tool for generating CRC's that could be modified for use as a pseudo-random sequence generator.
-- Gabor
Contributor
peter.a
Posts: 42
Registered: ‎10-26-2007
0

Re: Verilog code for a pseudo random sequence generator

What repetition rate do you accept for your 16-bit pseudo-random output?
Peter Alfke, Xilinx Applications
Peter Alfke
Director, Applications Engineering,
Xilinx San Jose
Xilinx Employee
barriet
Posts: 2,467
Registered: ‎08-13-2007
0

Re: Verilog code for a pseudo random sequence generator

Here are some useful resources to understand some of the theory and implementations of PRBS and related circuits:
http://www.xilinx.com/bvdocs/appnotes/xapp052.pdf (Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators)
http://www.xilinx.com/bvdocs/appnotes/xapp210.pdf (Linear Feedback Shift Registers in Virtex Devices)
http://www.xilinx.com/bvdocs/appnotes/xapp211.pdf (PN Generators Using the SRL Macro)
http://www.xilinx.com/ipcenter/catalog/logicore/docs/lfsr.pdf
http://vnsnes.freeshell.org/lfsr/index.html
 
Cheers,
bt
Visitor
dayueili
Posts: 18
Registered: ‎10-17-2007
0

Re: Verilog code for a pseudo random sequence generator

Thank you. I have successfully build one.
By the way, when I use $fopen to open a file and use $fdisplay to write data into it.
The file was generated but it's empty.
Why I couldn't see anything in the file?
Below lists a section of code, could anyone tell me anything wrong?

Regards,

D

integer fd;

    initial    // Clock process for clk_i
    begin
         fd = $fopen("d:\\Xilinx\\work\\test_mem\\prbs16bit.txt","w");
        #OFFSET;
        forever
        begin
            clk_i = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk_i = 1'b1;
            #(PERIOD*DUTY_CYCLE);
                $fdisplayb(fd,"%8b",FOUT);
        end
          $fclose(fd);
    end


Expert Contributor
gszakacs
Posts: 7,152
Registered: ‎08-14-2007
0

Re: Verilog code for a pseudo random sequence generator

Your $fclose statement comes after the forever loop, so it is never reached.  What happens to data written inside the loop depends on your operating system, but usually data is written out to the file in blocks.  When enough file output is available to fill a block (again block size is OS dependent) the block is written out to the file.  If you don't run the simulation long enough to fill a block, the file will be empty.  For some operating systems, closing the simulator will force the $fclose to write out pending data to the file.  Another possible behavior is to leave the file empty when the simulator is closed.  Are you using ModelSim under Windows?
-- Gabor
Visitor
dayueili
Posts: 18
Registered: ‎10-17-2007
0

Re: Verilog code for a pseudo random sequence generator

Thanks for your answer.
I'm using ISE simulator.
Visitor
dayueili
Posts: 18
Registered: ‎10-17-2007
0

Re: Verilog code for a pseudo random sequence generator

And yes, when I run the program long enough to fill in a block, you could see the content.
I'm using ISE simulator in Windows.


Expert Contributor
evgenis1
Posts: 352
Registered: ‎12-03-2007
0

Re: Verilog code for a pseudo random sequence generator

I've built a website - http://OutputLogic.com -  with online tools that generate a Verilog code for parallel CRC and Scrambler given data width and polynomial coefficients.

Also, there are short posts that describe an efficient parallel CRC/Scrambler generation algorithm for Verilog or VHDL.

 Hope that helps with what you need.

 
-evgeni