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There are many significant architectural improvements in the Xilinx UltraScale architecture and one of the benefits to be gained from these improvements is power consumption. The short video below demonstrates graphically how much power savings you can achieve through the use of various UltraScale enhancements—by directly comparing the performance of a Kintex-7 325T versus a Kintex UltraScale KU040 device configured with identical designs.

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Today marks the official release of the Vivado Design Suite, the 2014.1 edition. You should download and try this newest version if you’d like:

 

  • 5% better Fmax (on average)
  • 25% faster runtime with the Vivado pushbutton flow (on average) – Vivado was already fast and now, it’s faster
  • 1.5x overall speedup in simulation runtime (compile + simulation)
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Is execution speed a problem for you in your current system design? It usually is. If not, read on anyway.

 

 

Doulos Logo.gifNow’s your chance to get an hour’s worth of free, high-quality training from Doulos on using high-level synthesis and SystemC to move software tasks into hardware running on the programmable logic inside of Zynq All Programmable SoC. However, it’s not enough to merely transform the tasks into hardware modules, you must also model the hardware in SystemC/TLM-2.0 to ensure that performance meets expectations after the hardware is implemented. That too is included in this free online training. (Doulos authored the IEEE 1666 SystemC Language Reference Manual and the TLM-2.0 User Manual so they know a thing or two about this topic.)

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The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28

by Xilinx Employee ‎04-16-2014 10:49 AM - edited ‎04-16-2014 10:49 AM (119 Views)

In my last blog we had just arrived at the point where the benefit of using DMA (Direct Memory Access) had become obvious, although I previously alluded to the benefit of using DMA coupled with the AXI interfaces in Part 21 of this series.

 

Having reached this point, we’re left with the question mankind has long pondered: What exactly is DMA?

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Blackmagic Design builds entire family of $495 OpenGear converter boards from “low-end” FPGAs

by Xilinx Employee ‎04-15-2014 02:42 PM - edited ‎04-15-2014 02:47 PM (200 Views)

Blackmagic Design is a disruptive influence in the professional video world and I mean that in the best possible way. The Australian company’s 4K video cameras, like the $5995 URSA Super 35 4K digital film camera introduced last week at NAB 2014, are revolutionizing video work by dropping equipment costs. Blackmagic is so revolutionary that they publish their low list prices right in their elegant and stylish 203-page catalog, which I brought back with me after attending NAB 2014 in Las Vegas.

 

Most of Blackmagic Design’s products—especially the cameras—are neatly packaged so you can’t peek inside to see what chips they’re using. However, the company does have a line of ten converter boards designed for the OpenGear modular frame format developed by Ross Video and you can see such details on these bare boards.

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A fascinating article on the Electronics Weekly site, “Seeing SDR in action,” clued me into a pair of FPGA-based software-defined radio (SDR) boards from Ettus Research. The Ettus Research USRP B200/210 SDR Kits are fully integrated, single-board SDRs that communicate with a host PC through and are powered by a USB 3.0 interface. The boards cover a wide 70MHz-to-6GHz RF band and use open-source GNURadio software. The boards are based on the Analog Devices’ AD9361 2x2 RF Agile Transceiver and a Xilinx Spartan-6 XC6SLX150 FPGA.

 

 Ettus Research B210 SDR Board.jpg

 

Ettus Research B210 SDR Board

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Last week, EE Journal’s Kevin Morris published an article about the Xilinx “Softly-Defined Networks” announcement titled “‘Softly’ Defined Networks: Xilinx Punches Up the Programmability.” If you haven’t heard about this new version of SDN (software-defined networks), I’m not surprised. Softly-Defined Networks is a very new concept, announced only last week by Xilinx, that takes SDN a step further.

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Embedded Vision Summit West.gifThe Embedded Vision Summit West Conference, taking place on May 29 at the Santa Clara Convention Center, focuses on two Smarter Vision themes: recognition and autonomy. Under recognition, two presentations you might pay particular attention to are "Fast 3D Object Recognition in Uncontrolled Real-World Environments for Embedded and Mobile Applications" by Ken Lee of Van Gogh Imaging and "Programming Novel Recognition Algorithms on Heterogeneous Architectures" by Kees Vissers of Xilinx.

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FPGA-based i-movix X10 UHD Ultra Slow-Motion System accepts 1000fps in 4K, 2000fps in HD

by Xilinx Employee ‎04-14-2014 05:00 PM - edited ‎04-14-2014 05:18 PM (362 Views)

Super-slow-motion video has an unrivaled beauty that’s apparent as soon as you start to watch. I spent a few minutes last week at NAB 2014 with super-slo-mo expert Laurent Renard, founder and CEO of i-movix. His company had just introduced the 4K version of its X10 UHD slow-motion system, which works with the Vision Research Phantom Flex4K video camera. The i-movix X10 UHD is the first 4K ultra motion system to support both continuous super slow motion and ultra slow motion at frame rates of up to 1,000 FPS.

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Trade shows delivered serendipity long before the World Wide Web and that’s exactly what happened to me last week while walking the NAB 2014 show in Las Vegas. In a sea of 8K and 4K cinema and broadcast studio cameras, $20K zoom lenses, 4K video displays, advanced editing and color-grading consoles, and video-broadcast transmission products, I chanced upon the QPL Electronics Manufacturing Services booth. QPL, or Quality Production Limited, is located in Hillsboro, Oregon. The company specializes in turn-key manufacturing; provides program management, supply-chain management, manufacturing, and engineering services; and works closely with clients to manufacture pcbs in low and medium volumes. There were several such client boards in on display on the QPL booth. What caught my eye and made me stop for a conversation with QPL’s VP of Business Development Paul Forker was the appearance of Xilinx FPGAs on several of the boards on display. Two of the (obviously older) boards on display sported Virtex-4 FPGAs.

 

A third board with nine (!) low-end Spartan FPGAs really caught my eye.

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Agilent test tools help you verify DDR4-2400 JEDEC compliance and signal margin

by Xilinx Employee ‎04-14-2014 10:21 AM - edited ‎04-14-2014 10:24 AM (257 Views)

DDR4 design is ramping up and you might be feeling the need for a little help in this department. Are you? If you are, there’s help from Agilent in the form of a DDR4 interposer soldered between the DDR4 memory IC and the pcb and special N6462A DDR4 Compliance Test software that runs on the Agilent Infiniium 9000/90000 Series oscilloscopes. The interposer provides easy access to the DDR4 signals as close as possible to the actual DDR4 memory device. An example of the kind of information you get from this test setup appears below. This waveform was generated by a Xilinx Kintex UltraScale KCU105 eval board.

 

 

Agilent Infiniium 90000X DDR4 Compliance Test Result.jpg

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Absolutely "Fabless" – a book review

by Xilinx Employee on ‎04-11-2014 04:07 PM (431 Views)

SemiWiki’s Daniel Nenni and Paul McLellan published “Fabless: The Transformation of the Semiconductor Industry” a couple of months ago. I’ve just finished reading it and have to say that if you have anything to do with the semiconductor industry you need to read this book. Nenni’s and McLellan’s book is invaluable if only to document the history of the industry’s fabless semiconductor transformation.

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Ethernet Summit Logo.gifThe Ethernet Technology Summit is coming to Santa Clara at the end of the month and if you know you’re putting 10G, 40G, or 100G Ethernet under the bonnet of your next system design, then the April 29 High-Frequency Communications Design Track is probably for you. Pay particular attention to session H-12, “FPGA Solutions at High Frequencies.” Nothing gets you to the finish line as fast as an FPGA.

 

Register here, now.

 

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The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

by Xilinx Employee ‎04-11-2014 12:20 PM - edited ‎04-11-2014 01:30 PM (625 Views)

This latest instalment of Adam Taylor's blog shows the result of a fixed-point math function implementation in the ARM-based Zynq SoC's programmable logic.

 

Having looked at how we can implement fixed-point mathematics within the PL (programmable-logic) side of the Zync SoC in pervious blog posts in the MicroZed Chronicles series, we now focus on implementing these functions within a system and we will see the rather surprising results of doing so.

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H.265/HEVC video encoding consumes only half the bandwidth of H.264 encoding for the same video quality, which makes it essential for 4K2K video. Vanguard Video has developed an H.265/HEVC video codec that complies with the latest HEVC draft spec. Perhaps the most interesting aspect to this codec is that Vanguard has implemented a real-time version of it for 4Kp30 video in software (C and hand-tweaked, “to-the-max” assembly language for selected algorithms), which encourages comparison. The software version of the codec runs in real time on four 8-core Intel Xeon microprocessors and Barco-Silex has implemented the same encoder, coded in an HDL by Vanguard, on a Xilinx VC709 Connectivity Kit based on one Virtex-7 690T FPGA. Suitably encouraged, we’ll make some comparisons right here.

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Image Matters—a Belgian vendor of JPEG2000 accelerator boards to the broadcast, video production, and cinema industries—was demonstrating their new IM-X PCIe board family at this week’s NAB 2014. The board comes in three versions, all based on the same pcb layout. Here’s a photo and diagram of the board:

 

 

Image Matters IM-X JPEG2000 PCIe board.jpg

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Although it’s not a product, the HD-to-4K2K high-resolution video upscaler was developed at Xilinx as a demonstration of Vivado HLS synthesis tool’s ability so support rapid development of complex algorithms using C, C++, or SystemC. In this following 1-minute video, Girish Malipeddi from Xilinx explains how Xilinx engineers used Vivado HLS to develop the video scaler for this week’s NAB 2014 show in less than a month without using HDL descriptions. The entire algorithm was written in C and then Vivado HLS mapped the scaler’s C code to FPGA hardware without the need for manually written Verilog or VHDL code.

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When you ask technical people about why we need 4K video, you tend to get answers in terms of frame resolution, color gamut, and other such feature-oriented justifications.  Ah, but if you ask people actually using the 4K equipment in their businesses, you get a far better understanding. That’s the sort of understanding I acquired when I wandered into the Canon and Sony booths this year at NAB 2014.

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MIPI CSI-2 camera interface for FPGAs demoed at NAB 2014

by Xilinx Employee ‎04-08-2014 08:28 PM - edited ‎04-08-2014 11:39 PM (430 Views)

Last month, I wrote about a low-cost MIPI CSI-2 interface for FPGAs involving 6 external resistors. (See “How to Drive Multiple Live Cameras and Displays for Pennies—A Free IEEE Spectrum webinar.”) This low-cost way to interface multiple cameras and displays greatly enhances the ability of Xilinx All Programmable devices to be used at the heart of diverse Smarter Vision systems for all sorts of markets including automotive, industrial, and medical.

 

This month at NAB 2014 in Las Vegas saw the demo system, based on a Xilinx ZC706 Zynq SoC Evaluation Kit and developed by Xilinx Alliance members Xylon and Northwest Logic, on display at the Xilinx booth. Here’s a short video of Xylon’s Christian Grimm explaining the demo:

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The advantage of digital video is that there are a lot of things you can do with a digital video stream. The disadvantage: there are a lot of things you must to with the video stream.  I’m at NAB 2014 in Las Vegas this week and It’s all about digital video capture, manipulation, production, transmission, storage, and playback. The event consumes the entire Las Vegas Convention Center with booths holding the latest digital video cameras, high-resolution displays, production editing equipment, large and small digital-video storage devices, and all manner of transport and transmission equipment. Every major manufacturer you can think of is here to show its wares.

 

Xilinx also has a booth at NAB 2014. That’s because Xilinx All Programmable devices permeate the professional, high-resolution video and high-speed video-transport and -distribution markets from digital video cameras to SDI (serial digital interface) ports to 4K and 8K displays. A variety of design IP vendors offering the building blocks needed to create professional video equipment are also at NAB 2014. One of these is intoPIX of Belgium, a member of the Xilinx Alliance program.  

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FIRST Robotics Regionals in San Jose: What a blast!

by Xilinx Employee on ‎04-05-2014 07:43 PM (632 Views)

I attended the FIRST Robotics Regional competition held in the Events Center at San Jose State University today. The competition, now in its 23rd year, is the brain child of inventor Dean Kamen—think home dialysis machines, the Segway, intelligent Coke drink printers, and clean-water machine technology for the world—who decided that we needed a competition that celebrated STEM (science, technology, engineering, and math) skills in High School students the same way that sports teams celebrate athletic skills. There were 59 school teams participating in today’s regional meet. Most were from Northern California but one came from Honolulu, Hawaii and another from Bogota, Columbia.

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Two quick shots of Inrevium FPGA boards from this week’s EELive! conference in San Jose

by Xilinx Employee ‎04-04-2014 02:18 PM - edited ‎04-04-2014 02:34 PM (323 Views)

You might not have heard of Inrevium, a board-level brand from Tokyo Electron Device Limited, but they make some impressive FPGA-based development platforms. I saw two of these platforms in the Fidus Systems booth at this week’s EELive! conference in San Jose. The first such board is the TB-7V-2000T-LSI ASIC Development Test Platform, based on the Virtex-7 2000T 3D FPGA, which is the leading device—by far—for ASIC emulation because of its immense logic capacity. Here’s a photo of the Inrevium board at the EELive! conference:

 

 

Inrevium Virtex-7 2000T ASIC Development Test Platform.jpg 

 

Perhaps more useful is this block diagram of the board:

 

 

Inrevium Virtex-7 2000T ASIC Development Test Platform Block Diagram.jpg

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FPGAs and vision systems – demonstrably better performance, lower power consumption

by Xilinx Employee ‎04-04-2014 01:15 PM - edited ‎04-04-2014 01:18 PM (615 Views)

Carlton Heard at National Instruments has just published an extremely informative article on processing alternatives for machine vision titled “FPGAs – Taking Vision to the Next Level” in the latest edition of RTC Magazine. Heard writes:

 

“Vision applications must rely on alternative solutions to increase speed rather than simply depending on a faster processor. One option is to divide the image processing algorithm and do more in parallel, as many of the algorithms used in vision applications are very well suited to handle this. Technologies like SSE, hyperthreading and multiple cores can be been used to parallelize and do more without increasing the raw clock rate. However, there are issues when selecting this option. Unless the software package being used abstracts the complexity, there are difficulties in programming software to use multiple threads or cores. Data must be sent between threads, which can result in memory copies and synchronization jitter. Additionally, it is generally a manual process to take an existing single-threaded image processing algorithm and make it multicore compatible. Even then, cost often prohibits parallelizing very much because most system designers do not have the option to purchase a 16-core server class computer for each test cell they create.”

 

“The benefit of using an FPGA is that it is essentially software-defined hardware. Therefore, system designers can program the chip in software, and once that software is downloaded to the FPGA, the code becomes actual hardware that can be reprogrammed as needed. Using an FPGA for image processing is especially beneficial as it is inherently parallel. Algorithms can be split up to run thousands of different ways and can remain completely independent. While FPGAs are inherently well suited for many vision applications, there are still certain aspects of the system that may not be as suited to run on the FPGA. There are a number of features to consider when evaluating whether to use an FPGA for image processing.”

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Luke Miller’s latest SemiWiki blog is about the Red Pitaya open instrumentation platform and it’s fall-over funny if you’re amused by engineering humor. For example:

 

“The TeraTerm Screen was displaying all the usual CPU board goodies, more status you could shake a stick at. It even told me I was running a 20 out of 100 on the romantic scale, which is a new feature in Xilinx FPGAs called RomaticMon. You will not find that in…”

 

Here’s a photo of Luke running a spectrum analyzer app on the Red Pitaya with the display output broadcast to his Droid phone via WiFi:

 

 

Luke Miller Red Pitaya.jpg

 

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The National Instruments (NI) R Series multifunction RIO devices give you a fast way to implement a data-acquisition instrument or a closed-loop controller using the LabVIEW Graphical Programming Environment and a USB port on your desktop or laptop computer.

 

NI R Series multifunction RIO devices.jpg 

 

 

The six previously announced members of the NI R Series were based on the PXI interface and Xilinx Virtex-5 FPGAs. The four new products are all based on Xilinx Kintex-7 All Programmable devices, with significant increases in resources, particularly DSP resources, as you can see from this graph:

 

NI R Series RIO Table.gif

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This week at the EELive! conference in San Jose, National Instruments (NI)  won the EE Times and EDN ACE Award for Science, Technology, Engineering, and Math (STEM) Impact. NI has been a major contributor to STEM education for years. The company’s founder, Dr. James Truchard, holds STEM education very close to his heart and he has close ties to the University of Texas at Austin.

 

 

 Dr James Truchard Founder of National Instruments.jpg

 

Dr. James Truchard, Co-Founder, President, and CEO of National Instruments

 

 

Several of NI’s STEM education initiatives played a factor in winning this award:

 

  • Community involvement through in-classroom and extracurricular robotics mentorships
  • The introduction of NI roboRIO
  • The NI LabVIEW Campus Tour
  • NI LabVIEW K-12 Action Packs
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Open-source, laptop-style, multi-core ARM computing platform has hidden "fun feature": an FPGA

by Xilinx Employee ‎04-03-2014 10:48 AM - edited ‎04-03-2014 10:57 AM (1,137 Views)

Yesterday morning at the EELive! conference in San Jose, famed hardware hacker Andrew "bunnie" Huang presented a keynote that ended with his description of a fascinating experiment in open-source hardware and software development called the Novena computing platform. Novena is based on a quad-core ARM Cortex-A9 MPCore processor, embodied in a Freescale i.MX6 processor. Here’s a recent photo of the board:

 

 

Novena Computing Platform.jpg

 

Huang’s Novena computing platform runs Linux, with Debian being the default distribution.

 

The idea behind this board is to enable experimentation with laptop-sized hardware platforms. To that end, Huang has developed a very slick laptop-style case that he’s prototyping. There’s an air piston that pneumatically opens the case when you spring the latch. Very slick.

 

Huang showed a photo of the case during his keynote. “The paint was still wet” he said.

 

 

Novena Computing Platform in case.jpg

 

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This week at Interop in Las Vegas, Alpha Data and Xilinx are again demonstrating Xilinx OpenCL running a Monte-Carlo simulation based on the Black-Scholes financial market model developed back in 1973 by Fischer Black and Myron Scholes.  Alpha Data’s ADM-PCIE-7V3 FPGA board is accelerating the simulation using its on-board Xilinx Virtex-7 X690T FPGA.

 

 

 Alpha Data ADM-PCIE-7V3.jpg

 

 

The FPGA has been configured using the new Xilinx OpenCL design environment, first demonstrated last year at Supercomputing 2013 in Denver, Colorado. Moving the simulation from a CPU to the FPGA provides a 10x speedup in execution.

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This video of a live demo at EELive! (the show formerly known as the Embedded Systems Conference) shot today shows five picture-in-picture live-video images inserted and overlaid on a 1080p60 graphics screen, all generated by a Xilinx Virtex-7 XC7VX485T FPGA on a VC707 Eval Kit. The speaker in this short video is Scott Turnbull, Director of Technology at Fidus Systems of Ottawa. Fidus, a Xilinx Alliance Program Premier member, developed this demo. They’re a broad-spectrum systems design house and consultancy with a growing line of off-the-shelf FMC mezzanine cards too.

 

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Is DDR4 the last SDRAM protocol? Yes, says SemiWiki’s Eric Esteve. Then what are the alternatives?

by Xilinx Employee ‎04-01-2014 01:37 PM - edited ‎04-01-2014 03:15 PM (846 Views)

SemiWiki’s Eric Esteve just published a blog titled “Bye-Bye DDRn Protocol?” Esteve admits that his assertion is provocative and he admits that “DDR4 will most probably be used for years.” That’s clear from Intel’s recent announcement on March 19 of DDR4 SDRAM support in future processors. Instead of just announcing “support” in future products, Xilinx has already demonstrated DDR4 operation with the new Kintex UltraScale All Programmable devices. (See “Ready for DDR4-2400? Need the bandwidth? Need the lower power consumption? Watch this 8-minute video...”)

 

Esteve further confirms the solid position that DDR4 SDRAM will have over the next several years. He writes “We may expect that DDR4 will be used in the enterprise market for the next two years, then in the Desktop PC segment when the DDR4 memory device price will have come down to the same level, or below DDR3 devices.” When that happens, you can expect DDR4 SDRAM to break into the embedded arena as well because by then, it will not only deliver the highest DRAM performance but the lowest per-bit cost as well.

 

Nevertheless, writes Esteve, “the '4' in DDRn will certainly be the latest of this kind…” [sic, I think Esteve means "last of this kind" from the context.]

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About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, embedded systems design, design IP, EDA, and programmable logic.