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Intilop has just announced availability of its TCP Hardware Accelerator (a TCP Offload Engine or TOE)—which manages 16K concurrent TCP sessions—pre-ported and tested on an Alpha Data ADM-PCIE-7V3 card, which is based on a Xilinx Virtex-7 VX690T FPGA.

 

 

Alpha Data ADM-PCIE-7V3.jpg

 

 

Alpha Data ADM-PCIE-7V3 card, which is based on a Xilinx Virtex-7 FPGA

 

 

This offering provides ultra-low-latency (77 nsec) protocol acceleration at 10G line rates—orders of magnitude faster than software-based TCP implementations. Intilop is targeting this accelerator at data-center applications including Cloud Computing, Network Security, Telecomm, and server appliances in government and enterprise systems. Customers can add value through their own hardware IP using the “super simple” FIFO-based interface to the TCP Hardware Accelerator.

 

The $89 Xilinx Spartan-6 FPGA LX9 MicroBoard is another low-cost way to learn FPGAs

by Xilinx Employee ‎10-22-2014 11:41 AM - edited ‎10-22-2014 11:43 AM (559 Views)

 

Yesterday while Googling up some information for the blog about the miniSpartan6+ development board, I stumbled upon the $89 Xilinx Spartan-6 FPGA LX9 MicroBoard. I’m sure I haven’t written about this little FPGA development card, even though it’s been around for a while, so now’s the time. The Spartan-6 MicroBoard is a complete, low-cost way for you to get into FPGA development with Xilinx Spartan-6 FPGAs. It uses a USB port for both power and JTAG programming so all you need is a USB cable (included) and a host PC. Best of all, for someone like me, the board has a pre-loaded configuration so it can do something right out of the box. There’s also a series of video tutorials, Avnet Speedway Design Workshops, and an active Avnet support forum to go with this board.

 

 

Avnet Spartan-6 MicroBoard.jpg

 

 

Even though tiny, the Xilinx Spartan-6 FPGA LX9 MicroBoard includes:

 

  • Spartan-6 XC6SLX9-2CSG324C FPGA
  • 64Mbytes of LPDDR SDRAM
  • 128Mbits of Multi-I/O SPI Flash Memory
  • 10/100 Ethernet PHY
  • USB-to-UART port
  • On-board USB JTAG circuitry
  • Two Digilent Pmod compatible headers (2x6) for easy peripheral device expansion
  • Single-chip, 3-rail power with Power Good indicator
  • TI CDCE913 programmable VCXO clock synthesizer chip
  • Over-voltage and ESD protection on USB
  • Four programmable LEDs
  • 4-bit DIP switch
  • Reset and PROG push-buttons
Read more...

Napatech NT40E3-4-PTP and NT4E2-PTP.jpg

 

Dell OEM Solutions now offers 4G and 40G Napatech Acceleration Platforms based on Dell PowerEdge servers and Napatech PCIe accelerator cards. It is paired with the Dell PowerEdge R720 2S/2U rack server, which is based on Intel Xeon E5-2600 or E5-2600v2 processors. The Napatech NT40E3-4-PTP card used in the 40G Acceleration Platform is a 40Gbps accelerator with four 10Gbps SFP+ ports. It is paired with the Dell PowerEdge R620 2S/1U rack server, which is based on Intel Xeon E5-2600 processor. The Napatech NT4E2-4-PTP card used in the 4G Acceleration Platform is a 4Gbps accelerator with four 1Gbps SFP ports. Both Napatech accelerator boards used in the Dell Acceleration Platforms are based on Xilinx Virtex-7 FPGAs.

 

The boards provide full packet capture and analysis of Ethernet LAN data with zero packet loss for all frame sizes, providing intelligent features for flow identification, filtering, and distribution with extremely low CPU load. Flexible time synchronization support includes support for IEEE 1588-2008 (PTP v2).The accelerator boards are designed for in-line applications.

 

Dell OEM Solutions has helped customers in key vertical markets accelerate time to market through customizable Tier-1 OEM technologies for more than 15 years. The Napatech Acceleration Platforms are the latest products in the company’s line, designed for development of high-performance network management and security appliance products. These are pre-tested and pre-integrated products for the data center, so these platforms reduce the time needed to develop and deploy new products for that market.

 

 

 

For more information, download and read the White Paper titled “Dell and Napatech: Accelerating Appliances”.

 

 

For more information on how Napatech has developed these high-speed PCIe accelerator cards for data-center applications, see “FPGAs as business-model enablers: Napatech at the Ethernet Technology Summit.”

 

 

miniSpartan6+ Kickstarter FPGA dev board update + video of HDMI I/O and processing

by Xilinx Employee ‎10-21-2014 03:00 PM - edited ‎10-21-2014 08:30 PM (1,016 Views)

The latest update on Scarab Hardware’s miniSpartan6+ FPGA dev board, a funded Kickstarter project (11x over its funding goal), appears here. As you can see, they’re assembling boards:

 

 

miniSpartan6+ assembled boards.jpg

 

 

Shipping should commence this week. Meanwhile, there’s a video of the board being used to generate HDMI video and to input, process, and output HDMI video. The FPGA configuration for the HDMI processing and I/O is based on Mike Field’s FPGA work as posted on his Hamsterworks site.

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Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

by Xilinx Employee ‎10-20-2014 10:23 AM - edited ‎10-21-2014 12:44 PM (681 Views)

By Adam Taylor

 

As I discussed last week, Petalinux is the official Linux distribution for the Zynq SoC. To get the most out of this distribution, we need to be able to build our own version. This requires development on a Linux system. Now, not all of us develop on these systems so creating a new machine can be expensive and time consuming. I will therefore be using a Virtual Machine to provide access to the Petalinux distribution. I have used a similar approach previously to use the CERN libre Filter design tool and it has worked well for me.

 

I’ll be using the Oracle VM Virtual Box machine and creating an Ubuntu installation of Linux on this virtual machine. This is very simple to achieve. First, download the VM virtual box and an Ubuntu ISO onto the hard drive of your host machine.

 

Once you have installed the VM Virtual box the next step is to select new on the virtual box manager and create your virtual Linux machine.

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Best-in-class software development teams deliver embedded products with 0.1 bugs per thousand lines of code. They consistently beat the schedule without grueling overtime.

 

Does that sound like your team?

 

No? Then what actions are you taking to improve your team's results?

 

Hoping for things to get better won't change anything. Overly general platitudes like “trying harder” and “working smarter” never work.

 

What does work? Getting expert advice from people who have been there and done that.

 

My good friend Jack Ganssle is teaching his one-day seminar “How to Develop Better Firmware Faster” three times next month. Jack knows more ways to mess up software development than any three other people I know. Fortunately, he also knows how to deal with these problems and he’s been telling people how they can do the same for many years now.

 

If software bugs and other development nuisances are biting you, Jack’s one-day course will teach you practical—and proven—ways to develop better firmware faster.

 

What have you got to lose? A day of your time? The next major software bug will kill at least a week of your schedule. Best to call the exterminator now.

 

The three November classes will take place at:

 

Baltimore, MD – November 7, 2014

Santa Clara, CA – November 14, 2014

Germany (just outside of Stuttgart) – November 28th, 2014

 

Register here. Tell them Steve sent you.

COVE-2 CubeSat based on Space-Grade Virtex-5Q FPGA passes 6-month operations milestone

by Xilinx Employee ‎10-17-2014 01:13 PM - edited ‎10-17-2014 01:13 PM (823 Views)

 

By Patricia Steele, Xilinx Employee Communications

 

 

M-Cubed-COVE CubeSat.jpg

 

M-Cubed/COVE-2 CubeSat (Image Credit: University of Michigan)

 

 

In December 2013, University of Michigan - Ann Arbor in conjunction with Jet Propulsion Laboratories, California Institute of Technology, and NASA's Earth Science Technology office launched into space the M-Cubed/COVE-2 CubeSat (a mini satellite used for space-science research and technology verification). Onboard the CubeSat sits the Virtex-5QV (V5QV) FPGA. The Virtex-5QV is the first of its kind - combining rad-hard technology with re-configuration capability used for high-performance processing.

 

 

COVE Virtex-5Q Processor Board.jpg

 

 

The COVE FPGA processor board (Image Credit: NASA/JPL)

 

 

M-Cubed's mission was two-fold. The primary assignment was to validate the Technology Readiness Level (TRL) of the new, on-board hardware and software. Pending success, the secondary undertaking was to perform a Decadal Survey for Aerosol Science (describes the role of clouds and aerosols in climate changes that can affect global warming) for the Aerosol-Cloud-Ecosystem.

 

One of the new technologies was an algorithm designed for NASA's Multiangle Spectropolarimetric Imager (MSPI), a multi-directional, multi-wavelength, high-accuracy polarization camera that processes 95 Mbytes/second of raw video data. Additionally, the Virtex FPGA would reduce this data by two-orders of magnitude. With no loss of information and in real-time, data would then transmit back down to Earth.

 

After many months in orbit, M-Cubed's primary mission was a success. According to Dr. Charles Norton of JPL and Cal Tech, "We recently passed our 6-month minimum operations milestone and have already met all of the Level-1 flight requirements for the payload and the mission. [The] team has been tracking housekeeping data on the Xilinx V5QV, and the image-processing algorithm has performed flawlessly on the FPGA hardware throughout the flight experiment." With this success, Virtex has advanced the TRL for future space-based MSPI instruments. Thus, the secondary mission began. Today, the CubeSat continues to collect, process, and successfully send back massive amounts of compressed MSPI video and data to NASA.

 

Note: This story by Patricia Steele originally appeared on the internal Xilinx Crossroads employee site

Teardown Thursday: See the Zynq-based NI VirtualBench and Cloudium IMP torn apart live at ARM TechCon.

by Xilinx Employee ‎10-16-2014 04:33 PM - edited ‎10-16-2014 04:35 PM (769 Views)

Earlier this month at ARM TechCon, I had the pleasure of moderating a double teardown panel at ARM TechCon with Kyle Bryson, Principal Architect at National Instruments and John Hickey, CEO of Cloudium Systems. First, we tore apart the National Instruments VirtualBench, an All-in-One Benchtop Instrument that combines the functions of an MSO (mixed-signal oscilloscope), a logic analyzer, a digital multimeter, an arbitrary waveform generator, and a programmable power supply. There are also a few software-controlled digital I/O lines for creating test and control systems. Next, we tore apart a Cloudium Systems Integrated Media Platform, a small set-top-box-like, cloud-oriented server designed to handle multiple compressed video and audio streams.

 

Both of these products are based on the Xilinx Zynq SoC and the following video shows you how the two products were designed and constructed and what Zynq features were used to realize the designs.

Read more...

According to this Mathworks press release, the latest MATLAB Release 2014b adds direct Xilinx Vivado integration to the package’s HDL Coder and Vivado support for FPGA-in-the-loop verification to HDL Verifier.

 

New Zynq-based SDR Reference Design supports Public Safety and Military LTE Radio Development

by Xilinx Employee ‎10-14-2014 06:15 AM - edited ‎10-14-2014 06:20 AM (1,520 Views)

Avnet Zynq 7000 SDR Eval Kit.jpg

Xilinx and SAI Technology have announced the availability of the first LTE UE (User Equipment) Software Defined Radio (SDR) reference design based on the Xilinx Zynq All Programmable SoC. The reference design can be used to develop public safety radios capable of voice, image, and video communications and has been implemented using the Vivado HLS (High-Level Synthesis) tool to make it easy for SDR developers to customize all protocol layers using high-level programming-language descriptions. You can immediately start working with this reference design using the Zynq-7000 All Programmable SoC/AD9361 Software-Defined Radio Systems Development Kit available from Avnet.

Leigh and Branham Robotics teams at the STEM Encampment 2014.jpgSeveral hundred Bay Area Boy Scouts and Cub Scouts passed through the Xilinx booth at the San Francisco Bay Area Council STEM (Science, Technology, Engineering, and Mathematics) Encampment, a day-long event held at the Alameda County Fairgrounds in Pleasanton on Saturday, October 11. Xilinx participated in the STEM Encampment to help these young people and their parents learn about the company and some of its youth-oriented community support activities and about Xilinx products, the semiconductor industry, engineers and engineering. David Manley and Steve Leibson from Xilinx staffed half of the company’s double-wide booth and explained the world of Xilinx and engineering to an endless stream of young people ranging from preschool to High School age. Several student members of Xilinx-supported robot teams from Leigh and Branham High Schools in San Jose occupied the other half of the Xilinx STEM Encampment booth. They were the real stars of the event, getting the lion’s share of the attention in the Xilinx booth with their live robotic games and activities.

Read more...

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

by Xilinx Employee on ‎10-13-2014 10:09 AM (1,439 Views)

 

By Adam Taylor

 

Having spent the last few blogs looking at operating systems and AMP (asymmetric multiprocessing), a natural progression is to look at running Linux on the MicroZed. We’ve not yet discussed running Linux on the Xilinx Zynq SoC. Linux has become a major embedded operating system so by discussing it now, we’ll also be discussing symmetric multiprocessing, killing two birds with one stone—so to speak.

Since its creation by Linus Torvalds—who wrote Linux as a personal project in 1991 while he was a computer science student at the University of Helsinki—Linux has become one of the world’s most widely adopted operating systems and has become increasingly popular as an embedded OS. With a large number of software developers now familiar with both the Linux kernel and application development for Linux, it stands to reason that we would wish to run Linux on the PS side of the Zynq SoC.

 

Linux is capable of running on one ARM Cortex-A9 MPCore processor core or on both of the cores in the Zynq SoC. When we run the OS on both cores, a single operating system is in control and this makes it an SMP (symmetric multiprocessing) system.

Read more...

Adrian Cosoroaba and Terry Magee from Xilinx are giving a talk titled “High Performance DDR4 interfaces with FPGA Flexibility” at 2:40pm on October 15—next week at Memcon at the Santa Clara Convention Center. Magee, a Principal Engineer at Xilinx, architected the DDR4-2400 PHY used in the new Xilinx UltraScale All Programmable FPGAs and the talk will discuss how the Xilinx PHY design team put together a reliable DDR4-2400 memory interface with the extreme flexibility (compared to an ASIC) and low power consumption required by programmable FPGA I/O pins.

 

The demanding DDR-2400 capabilities had to be added without compromising the I/O pin’s ability to perform other tasks as challenging as operating as a high-speed serial I/O port or as simple as an LED driver. In addition, the same high-speed PHY would be expected to drive DDR3-2133, DDR3L-1866, and LPDDR3 SDRAM; low-latency RLDRAM 3; and QDRII+ and QDR IV SRAM. That’s a tall order for one I/O pin yet it’s the sort of capability and flexibility that FPGA PHY designers are expected to create.

 

The solution to developing a DDR4-2400 PHY was to “turn the problem on its head,” to steal a line from one of the presentation slides. I’m not going to tell you how that was done—not just yet—because I’ll steal no thunder from next week’s presentation. I will tell you it’s not nearly as simple as purchasing a 3rd-party PHY IP block and dropping it into the design.

 

However, I will give you a graphical preview:

 

 

UltraScale DDR4-2400 PHY Eye.jpg

 

 

Interested? Register by clicking here. (It’s free.)

Do you need a clear understanding of the advantages and disadvantages of FPGAs, NPUs, and Multicore CPUs for packet processing? You will get one at the Linley Processor Conference 2014 in Santa Clara. Atul Shinde from Xilinx will be speaking about “Partitioning Hardware and Software Programmability for Best Carrier Ethernet Processing” on the first day of the conference, October 22, and I’ve stolen the following slide from his slide deck as a taste of what he’ll be discussing:

 

 Packet Processing Programmability Comparison.jpg

 

 

Shinde’s slide lists five major dimensions for the purpose of comparison:

 

  1. Description portability: You face extra work if you need to change your system description to fit the implementation hardware.
  2. Packet processing flow: If the implementation hardware does not match the natural flow required for packet processing, you face bottlenecks and resource conflicts.
  3. Lookup tables: Fixed-size memories in a hardware implementation lead to wasted resources and access conflicts.
  4. QoS policies: Poor implementation granularity leads to sub-optimal scaling and a lack of needed flexibility.
  5. Proprietary IP: If your packet processing requires anything special, you’ll incur additional hardware or suffer the inefficiency of software-based processing using NPUs or Multicore CPUs.

 

Don’t believe it? Register for the conference and make Shinde prove it to you.

 

Registration for pre-qualified attendees is free if registration forms are received by October 16, 2014. Registration for non-qualified attendees is $795 if received by that date. On-line registration closes on Thursday, October 16 at 5 PM Pacific.

 

Vivado 2014.3 adds more than 40 OpenCV functions from Auviz Systems

by Xilinx Employee ‎10-08-2014 01:26 PM - edited ‎10-09-2014 06:24 AM (1,352 Views)

The new Vivado Design Suite 2014.3 supports more than 40 OpenCV functions, now available from Xilinx Technology Ventures portfolio company and Xilinx Alliance Member Auviz Systems through Vivado HLS, the C-based synthesis tool in the Vivado Design Suite.

 

You can download Vivado Design Suite 2014.3 now, here.

 

More than 1400 people read last month’s blog post “JESD204B ADC interface magically commutates Gsamples/sec into a polyphase channelizer,” which described how ADCs with a JESD204B interface can commutate or decimate a Gsample/sec+ data stream into multiple lower-rate streams for parallel processing with a polyphase channelizer. If you understand that last sentence, then you will be delighted to learn that there is now a configurable Super Sample FIR filter in the latest release of the Xilinx System Generator, which you will find in the latest Vivado 2014.3 release.

 

 

Super Sample FIR Filter in Vivado 2014.3.jpg

 

Old joke from the original "Blues Brothers" movie: We have both kinds of music here—country and western.

 

The Zynq SoC gives you three major forms of programmability: software, hardware, and I/O. When you choose to use a Zynq SoC for the heart of a system, you get an expanded number of design choices—a very large design space to explore—and your real-time application’s performance depends on your team making the right choices in that design space. Xilinx has just posted a new 211-page document called “The UltraFast Embedded Design Methodology Guide” (UG1046) that will help your team make these choices using industry’s best design practices.

The User Guide dedicates chapters to:

 

 

UltraFast Embedded Design Methodology Guide.jpg

 

 

  • System-level design considerations
  • Hardware design considerations
  • Software design considerations
  • The hardware design flow
  • The software design flow
  • Debugging

 

It ends with a guide to additional Xilinx design resources.

 

The guide is free and is one click away. Click here.

Today’s release of the Vivado Design Suite 2014.3 for Xilinx 7 series All Programmable devices, Zynq SoCs, and UltraScale FPGAs includes a ton of enhancements and performance improvements. Here are a few:

 

  • If you’re looking for more performance, you’ll get significantly higher average Fmax from the new release.

 

  • If you want better QoR, you’ll see a substantial reduction in on-chip resource consumption for both RTL and HLS flows.

 

  • If you want faster runtime, you’ll find multi-core CPU support in Vivado 2014.3 and physical optimization is now multithreaded.

 

  • If you want easier AXI4 integration, you’ll find a fully automated way to connect different AXI4 flavors (memory-mapped versus streaming) by just wiring them together.

 

  • If you would like a more unified simulation environment, it’s there.

 

 

In addition, there’s a new UltraFast Embedded Design Methodology Guide, UG1046.

 

More detailed blogs about specific new features will follow shortly.

Read more...

I just found out that Doulos and EnSilica will be giving a free, 1-hour technical Webinar on October 10 to help you integrate your custom HDL IP into Xilinx Zynq SoCs so that the IP plays nice with the on-chip, dual-core ARM Cortex-A9 MPCore processors via the AXI interfaces. There are several convenient Webinar times during the day for India, Europe, and North America. Can’t beat the price--free. You have three days to register. Better hurry.

 

Register here, now.

Learn to debug and validate DDR3/DDR4 SDRAM designs in 1-day Keysight class, Oct 21 in Santa Clara

by Xilinx Employee ‎10-07-2014 02:49 PM - edited ‎10-07-2014 03:01 PM (960 Views)

Looking down the barrel of a DDR4-2400 or a fast DDR3 SDRAM design? Want some help? Keysight (formerly the T&M piece of Agilent) is giving a free, 1-day design seminar titled “Gain insight into DDR3/4 and LPDDR3/4 Signal Flow” in Santa Clara, California on October 21. This is a live class and promises to be well work a day of your time. It’s being taught by Jennie Grosslight, Keysight’s Memory Test Product Manager. I met her at DesignCon earlier this year. (See “Avoid the three pitfalls of designing with DDR4 SDRAM – Live from DesignCon 2014.”) If I was going to design a DDR4-baseed design, I’d want Jennie’s help. If you attend this class, you’ll understand why.

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MemCon Logo.jpgThe annual MemCon conference takes place in Santa Clara next week, October 15, in Santa Clara, CA. If you’re designing with any kind of new memory device—DDR4, LPDDR4, DDR3L, Wide I/O, etc—then you ought to dedicate a day to this great event. I guarantee you’ll learn something. (I once ran this event, so I personally vouch for its value.)

 

 

If you’re connecting FPGAs or the Zynq SoC to fast memories, you’ll also be happy to know that Xilinx will be at this event again this year. But of course, that’s why I’m writing about it in Xcell Daily.

 

Click here to register. It’s free.

 

 

 

By Adam Taylor

 

 

Well I must admit that this is one blog post I never expected to write. When I started writing the MicroZed Chronicles, I was never sure I would be writing the 52nd weekly instalment. Having achieved this milestone and more than 150,000 views along the way, I would like to look back over the year and review what I have covered on the Zynq SoC. I’ll then outline a few of my plans for the future.

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Aquantia’s newly announced AQrate technology—as embodied in the company’s AQR405, AQR205, and AQR105 Quad/Dual/Single AQrate PHYs—can instantly boost cabling infrastructure bandwidth by 5x by transforming existing cable infrastructure based on Cat 5e and Cat 6 cabling into fully functional 5Gbps networks. Essentially, you unplug all of those 1Gbps Ethernet line cards, replace them with 5Gbps line cards, and your data center now runs 5x faster. No cable changes. No forklift upgrades. Nada.

 

Aquantia’s AQrate PHY technology drives 5Gbps over 100m of existing Cat 5e and Cat 6 cabling. That’s truly a big deal.

 

 

Aquantia AQrate PHYs.jpg

 

 

5G Ethernet isn’t an IEEE standard and you’re not going to find off-the-shelf Ethernet ASSPs to drive Aquantia’s ingenious new AQrate PHY chips at that data rate. Ah, but Xilinx All Programmable devices and IP portfolio already support Aquantia’s AQrate technology, even though it was announced yesterday. Xilinx has been collaborating with Aquantia in preparation for this week’s announcements.

 

Note: Aquantia is an investment portfolio company of Xilinx Technology Ventures—the investment arm of Xilinx, Inc.

 

FPGA-based SDR transceivers revive 36-year-old NASA ICE space probe, for a while

by Xilinx Employee ‎10-06-2014 12:29 PM - edited ‎10-06-2014 12:33 PM (1,448 Views)

Perhaps you’ve heard about the crowdfunded attempt to revive NASA’s International Sun/Earth Explorer 3 (ISEE-3), launched on August 12, 1978. This wandering spacecraft was retasked and became the first to pass through a comet’s tail in 1985. By then, it was renamed the International Cometary Explorer (ICE). Eventually, project funding dried up and the spacecraft was decommissioned. However, its solar power systems and radio transponder continued to operate. NASA’s Deep Space Network detected the ICE space probe in 2008.

 

 

NASA ISEE-3.jpg

 

 

NASA’s ISEE-3 Spacecraft

 

 

As a consequence of that communication, Dennis Wingo (Skycorp Inc) and Keith Cowing (Space College/Spaceref) formed the ISEE-3 Reboot Mission and launched it as a crowdfunded project on RocketHub. The idea was to recommission the spacecraft, fire its engines, put it in Earth orbit, and perform new science along the lines of the original mission goals using this antique piece of space gear. The crowdfunding project reached and exceeded its funding goal, raising $159,502. The project’s mission control took residence in an abandoned McDonald’s restaurant (Building 596) adjacent to NASA’s Ames Research Center at Moffat Field near Sunnyvale and Mountain View, California. (This same restaurant, now dubbed “McMoon’s,” was used to recover video from the 1960’s-era Lunar Orbiter mission seven years earlier.)

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Cornerstone Identity exhibits pocket-sized, Zynq-based iris ID scanner at ARM TechCon 2014

by Xilinx Employee ‎10-06-2014 10:45 AM - edited ‎10-06-2014 10:45 AM (1,800 Views)

Cornerstone Identity exhibited a pocket-sized, Zynq-based iris ID scanner at last week’s ARM TechCon 2014 in Santa Clara. The small device images an eye and can identify a person using iris recognition at imaging speed, thanks to the iris-recognition hardware residing in the Zynq SoC’s PL (programmable logic). Here’s a photo of the scanner sitting atop some clear blocks:

 

 

 

Cornerstone Identity Iris Scanner.jpg

 

 

 

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Today is Teardown Thursday at ARM TechCon in Santa Clara: 11:30 am

by Xilinx Employee ‎10-02-2014 06:13 AM - edited ‎10-02-2014 06:16 AM (1,258 Views)

Just a quick reminder: if you're at ARM TechCon, we're tearing down two really interesting Zynq-based products today at 11:30 am in the exhibit floor in the Expo Theater back in the far right corner of the exhibit space.

 

Oh, and we're giving away one National Instruments VirtualBench combo instrument to a lucky attendee. Unfortunately, as emcee I don't qualify to win.

 

See you there.

 

 

Giveaway News Flash for ARM TechCon! NI to give away a $1995 VirtualBench at Teardown Thursday

by Xilinx Employee ‎09-30-2014 04:45 PM - edited ‎09-30-2014 05:06 PM (1,577 Views)

I just found out that National Instruments will be giving away one Zynq-based $1995 NI VirtualBench, a virtual instrument suite, at the 11:30am ARM TechCon Teardown Thursday event this Thursday, October 2. It won’t be the one we tear down. The NI VirtualBench incorporates the features of a mixed-signal oscilloscope, function generator, logic analyzer, DMM, programmable dc power supply, and a set of programmable digital I/O control lines in one compact package that won’t consume very much bench space. It uses either a PC or a Tablet as its user interface.

 

 

NI Virtual Bench Photo.jpg

 

 

Teardown Thursday takes place at the ARM TechCon Expo Hall Theater on the exhibit floor. You need to come by if you want a chance to win this.

 

If you’re interested in 400GE (400Gbps Ethernet) then you’re likely headed to the WDM (aka the Next Generation Optical Networking) Conference Dallas 2014, which opens on October 7. While there, be sure to stop by the Xilinx stand (#23) to see a Spirent 400G Ethernet Test System connected to a Xilinx VCU109 Evaluation Board based on the Xilinx Virtex UltraScale VU095 FPGA board with four sets of 100Gbps Sumitomo Electric CFP4 LR4 optical modules plugged in. The Xilinx VU095 FPGA provides the high-speed SerDes ports needed to connect to the optical modules, the 400GE MAC and PCS IP needed to implement pre-standard 400Gbps Ethernet, and a packat generator/checker to create and monitor 400GE traffic. The Spirent tester, also based on Xilinx FPGAs, contains four sets of 100Gbps Oclaro CFP2 LR4 modules so there’s some optical interoperability being demonstrated as well.

 

 

Spirent and Xilinx WDM 2014 demo.jpg

 

 

Note:

 

For more information on the Spirent 400GE tester, see “Getting to 400G Ethernet: Inside the Spirent 400G Ethernet Test System.”

 

For more information on implementing 400GE with FPGAs, see “Huawei’s 400GE router successfully completes testing on Spirent’s new 400GE test platform—both enabled by the Virtex-7 H870T 3D FPGA.”

Developing big IP? Get this FPGA-based IP Prototyping Kit

by Xilinx Employee ‎09-29-2014 04:37 PM - edited ‎09-29-2014 04:59 PM (1,450 Views)

If you’re developing large IP blocks, then S2C has something to help you accelerate development: the AXI-4 Prototype Ready Quick Start Kit based on the Xilinx Zynq SoC and Xilinx Virtex-7 2000T 3D FPGAs. The Quick Start Kit couples a Xilinx Zynq ZC702 Evaluation Board to an S2C TAI Logic Module as showing in the following diagram:

 

S2C AXI-4 Prototype Ready Kit.jpg 

 

The Xilinx ZC702 Evaluation Board has an on-board Zynq Z7020 SoC with a dual-core ARM Cortex-A9 MPCore processor and a programmable logic capacity of 85K logic cells—equivalent to approximately 1.3M gates. The S2C Quick Start Kit expands this capacity by extending the Zynq SoC’s AXI-4 bus through an interface module to one or more external Xilinx Virtex-7 2000T 3D FPGAs on the S2C TAI Logic Module. Each Virtex-7 2000T FPGA has a capacity of 1,954,560 logic cells—a 23X expansion in programmable-logic capacity per FPGA. This added programmable-logic capacity allows designers to quickly leverage a production-proven, AXI-connected prototyping platform with a large and easily scaled logic capacity – all supported by a suite of prototyping tools from S2C.

 

A demonstration of the Kit will be shown at the S2C booth at ARM TechCon 2014 in Santa Clara, CA on October 1-3.

 

Note: For more information about S2C’s prototyping tools, see the Xcell Daily blog post “TAI Player Pro 5.1 prototyping tool automatically partitions very large designs across multiple Virtex-7 3D FPGAs.”

 

This week, it’s Teardown Thursday at ARM TechCon in Santa Clara. Hope to see you there!

by Xilinx Employee ‎09-29-2014 10:48 AM - edited ‎09-30-2014 04:41 PM (1,370 Views)

This week’s ARM TechCon in Santa Clara at the convention center. On Thursday at 11:30am, we’ll be tearing down two very interesting Zynq-based products on the exhibit floor. I suspect you won’t want to miss the event because I know there will be design tips galore revealed during these teardowns.

 

First, we’ll be pulling the covers off of the National Instruments VirtualBench, a many-instruments-in one-box product. (Something I’ve wanted to do ever since the product was announced a year ago.) The NI VirtualBench incorporates the features of a mixed-signal oscilloscope, function generator, logic analyzer, DMM, programmable dc power supply, and a set of programmable digital I/O control lines in one compact package that won’t consume very much bench space. It uses either a PC or a Tablet as its user interface.

 

 NI Virtual Bench Photo.jpg

 

National Instruments VirtualBench

 

 

The second product we’ll open up is the Cloudium Integrated Media Processing Platform, a fanless video compression/decompression box designed to move HD video and audio bidirectionally through the Internet and through the cloud with maximum efficiency. The box we’ll be opening up is called the Cloudium Systems Zero Client and the Zynq SoC inside the box provides flexibility that allows users to upgrade to new protocols easily without opening the box. But we’re going to open it anyway.

 

 

Cloudium Systems Zero Client.jpg 

Cloudium Systems Zero Client

About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.