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By Tamara I. Schmitz, Director of Memory and Power, Technical Marketing, Xilinx


A seismic shift is shaking up the memory landscape. The cause for this shift is the fact that the line of incredibly popular DDR memories, a fundamental buffer used by 90 percent of Xilinx customers, will end with DDR4. This is not cause for immediate panic—DDR3 has a comfortable address on the majority of system boards (see the figure below showing the RAM usage by Xilinx MIG—Memory Interface Generator—users) and DDR4, though ramping slowly, will replace some of those sockets and serve them for years to come. Still, with the knowledge that DDR4 has no natural successor, customers are eyeing the next crop of memories and mulling over trade-offs such as bandwidth, capacity or power reductions. The likely successor is LPDDR3/4, with certain application spaces preferring serial DRAM solutions such as Hybrid Memory Cube (HMC).


By Romi Mayder, Director of Technical Marketing, Xilinx



Two years ago, a report by IEEE concluded that if current trends continue, communications networks will need to support capacity requirements of 1Tbps per second by 2015 and 10 Tbps by 2020. By next year, there will be nearly 15 billion fixed and mobile networked devices and machine-to-machine connections, according to the July 2012 report. For optical transport network (OTN) applications, the bandwidth per wavelength in a core node is expected to be in the range of 100G to 400G in 2015, rising to approximately 400G to 1T in 2020.


Many companies have expressed the need for 1Tbps applications for networking. These applications require transceivers that can directly drive 25G/28G backplanes due to reasons of routability, crosstalk, differential insertion loss and impedance matching, among others. Xilinx Virtex UltraScale devices surmount these challenges and support 1Tbps applications by enabling 25G/28G backplane operation without a retimer.


What does 20nm really buy you as a system designer? All by itself, perhaps not too much. But if you use advanced 20nm IC process technology as an architectural enabler as Xilinx has done with the mid-range Virtex UltraScale and high-end Kintex UltraScale All Programmable Device families, you get some pretty compelling value metrics for systems design.


Consider the following five system-level design scenarios:


  1. Migration from Virtex-7 All Programmable Devices to 20nm UltraScale devices: You will see 1.5x to 3x more performance per unit cost across the board with power reductions of 25% to 45%.
  2. Integration of multiple chips into one 20nm UltraScale All Programmable device: You will see as much as a 60% BOM-cost reduction.
  3. For system designs with heavy DSP use: You may well find that you can use mid-range 20nm Kintex UltraScale devices where you previously had to use high-end Virtex-7 devices.
  4. For systems already using Kintex-7 devices: You will get 25% to 120% more DSP capability and 1.5x to 4x more serial I/O bandwidth with 20nm Kintex UltraScale devices. You’ll also get power reductions of 25% to 45%.
  5. For applications with insatiable appetites for performance that are already using Virtex-7 devices: You will get double the system performance, lower power consumption, and you may see BOM costs drop by as much as 50%.


If one of these five scenarios applies to your team’s next project, you might want to read “UltraScale: Multiplying the Value of 20nm – Doing More for Less,” which explains more about the value of the Xilinx UltraScale architecture implemented in 20nm. Below is a table taken from this document with a far more detailed list of the 20nm UltraScale benefits:



Value of UltraScale.png UltraScale Migration Paths.png





When you design an SoC, you need to find the bugs in that design—fast—and the fastest way from Point A to Point B these days is FPGA emulation, which can run actual SoC firmware far faster than can software-based emulators. That’s just what you need for software development, hardware verification, hardware/software integration, and regression testing of complex SoCs. Cadence has just introduced its second-generation, FPGA-based Protium rapid prototyping platform. The Cadence Protium rapid prototyping platform is based on Xilinx Virtex-7 2000T 3D FPGAs. (See “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W.”)  There are four versions of the platform, with 2, 4, 6, or 8 of these Virtex-7 2000T 3D FPGAs. Here’s a comparison chart of the four rapid prototyping systems from the Protium data sheet:


 Cadence Protium Comparison Chart.png



Compared to Cadence’s 1st-generation Rapid Prototyping Platform (RPP), Protium offers 4x the gate capacity and 3x the memory, so you can tackle much bigger projects with this family of rapid prototyping platforms. Cadence has also given this 2nd-generation Protium platform the design flow from its much bigger brother, Cadence’s Palladium XP Verification Computing Platform, which the company says results in a 5x compile-time speedup.


As Cadence’s Richard Goering writes in his Industry Insights blog:


“The big problem with FPGA-based prototyping is bring-up time - that is, everything that it takes to compile an ASIC design into multiple placed, routed, and verified FPGAs that fully represent system functionality. ‘It is very important to bring up your prototype very quickly, because every week takes time away from when you can really use it,’ said Juergen Jaeger, senior product manager at Cadence. ‘Our goal is to shorten the bring-up time for FPGA prototypes from months to weeks.’”


According to Goering’s blog, the Protium platform offers three performance modes:


  • A fully automatic mode with automated ASIC memory mapping, partitioning, and FPGA placement and routing that runs at 5-10MHz.
  • A manually-guided mode that takes SoC-partitioning information from the design team and runs 20-50MHz.
  • A "black box" mode that places the SoC design in one Xilinx Virtex-7 2000T 3D FPGA and runs at more than 100MHz.


Here’s a diagram of the design flow using the Protium emulation platform:



 Cadence Protium Design Flow.png




As the diagram shows, the Palladium design front end now serves both the Palladium (on the left in the dashed box) and Protium (at the bottom) platforms. This unified design flow joins the two tools more closely than before.

Convey Computer Image Resizing Server.jpgConvey Computer’s new Accelerated Image Resizer is an FPGA-based PCIe card dedicated to resizing images, which needs to be done surprisingly often. Web servers are constantly serving up thumbnail versions of online images for social-media sites, searches, various forms of e-commerce including online catalogs, and many other Web applications.


The computational load for all of this picture manipulation has fallen on conventional Web server processors, which are not well matched to this task because image resizing is computationally expensive—shrinking a 12Mpixel image to thumbnail size can take 1.5 seconds on a server CPU. Multiply that by the many thousands of images that must be served up every minute of every by Web servers and there’s a real need for acceleration.


Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

by Xilinx Employee ‎07-21-2014 10:22 AM - edited ‎07-21-2014 10:23 AM (328 Views)

By Adam Taylor



The last few blog posts in the MicroZed Chronicles have looked at RTOS concepts. Having introduced these fundamentals, it’s time to implement our first OS on the Zynq-based MicroZed. That’s going to be Micrium’s uC/OS-III RTOS. (Note: Micrium’s uC/OS-II RTOS is in the Mars Curiosity Rover running one its analytical labs.) This blog will show you how to get the demo up and running.


Successful Platform Business Strategies: Getting Buy-in at All Levels of the Enterprise

by Xilinx Employee ‎07-17-2014 02:50 PM - edited ‎07-21-2014 04:21 PM (343 Views)

By Mike Santarini, publisher, Xcell Journal


The following is a companion article to the cover story in Xcell Journal issue 88, which gives a comprehensive cost-benefit analysis of silicon platforms comparing Xilinx’s Zynq-7000 All Programmable SoC as a platform to platforms implemented on ASICs and ASSPs.


Employing platform-based business strategies at any level of the enterprise can improve profitability, but when employed at every level of the enterprise, they can have a dramatic, compounding effect on profitability—creating prolific profitability. The companies that have most effectively deployed platform  strategies have woven platforming into their company’s DNA and have buy-in at all levels of an enterprise—from executives, to architects, engineers, and purchasing. Let’s look at how each of these roles within an enterprise contributes to creating prolifically profitable enterprises.


Logitraxx, the FPGA-based tracked robot kit, returns to Kickstarter. Act quickly and get it for $165

by Xilinx Employee ‎07-17-2014 11:06 AM - edited ‎07-17-2014 01:17 PM (1,031 Views)

If you’re looking to get a jump on developing the Skynet robots from “The Terminator” movie series, you will welcome the return of the FPGA-based Logitraxx Tracked Robot Kit and Development Platform on Kickstarter. The kit from SL Interphase is based on a Xilinx Spartan-6 LX9 FPGA, which will give you plenty of opportunity to experiment with motor control, autonomous vehicles, and sensor applications.


NI’s new Zynq-in-a-box SOM targets embedded development with dual-core ARM Cortex-A9

by Xilinx Employee ‎07-17-2014 09:30 AM - edited ‎07-18-2014 10:49 AM (1,423 Views)

NI (National Instruments) has just introduced yet another in its growing line of design and development products based on the Xilinx Zynq All Programmable SoC. This new offering is the NI sbRIO-9651 SOM (system on module) which consist of a fairly small pcb encased in a block of milled, black-anodized aluminum; 512Mbytes of DRAM; 512Mbytes of nonvolatile memory; the NI Linux RTOS; a debugged and ready-to-run BSP (board support package); and a complete set of middleware. NI says that this package significantly reduces development time, development risk, and time to market for a range of embedded system designs. Here’s a quote from the NI press release:


““We have evaluated several SOMs and embedded SBCs, and there is no comparison to the software integration offered by NI,” said Sebastien Boria, R&D mechatronics technology leader at Airbus. “We estimate that our development costs with the NI SOM are a tenth of the costs of alternative approaches because of the productivity gains of NI’s approach to system design, in particular to NI Linux Real-Time and LabVIEW FPGA.”


A 10x improvement in development costs is pretty hard to ignore.


A multidisciplinary team of scientists at the South Pole recently stared into the afterglow of the Big Bang. The team announced on March 17 that the BICEP2 experiment had collected the first evidence of gravity waves in the B-mode polarization of the cosmic microwave background (CMB).


Now scientists are looking for yet another fingerprint: evidence of gravity waves as recorded in the faint polarization spirals of CMB microwave photons. Finding these spirals would seem to confirm the inflation aspect of Big Bang theory—the idea that the universe expanded much faster than the speed of light long before the universe was even a picosecond old. In theory, this superluminal (faster than light speed) cosmic inflation created gravity waves that were embossed into the polarization of photons from the Big Bang.


The special camera the team is relying on to search for gravity waves uses transition-edge sensor (TES) bolometers to measure both E-mode (curl-free) and B-mode (gradient-free) microwave radiation. The camera is built around a second-generation McGill University DFMUX board based on Xilinx Virtex-4 FPGAs.


Astrophysicists elsewhere are using the same Xilinx board in their own experiments, while other researchers are trying out a new version of the camera updated with Kintex-7 devices. The Kintex version is also part of a mammoth telescope that Canadian scientists will use to investigate dark energy.





The polarization variation in the CMB microwave photons is called the B-mode signal and the signature is extremely faint. While the overall CMB black-body temperature is 2.73 Kelvin, the B-mode signal is roughly one 10 millionth of a Kelvin.


The B-mode signal is generated at small angular scales by the gravitational lensing of the much larger, primordial “E-mode” polarization signal, and at large angular scales by the interaction of the CMB with a background of gravitational waves produced during the Big Bang’s inflationary period.

B-mode polarization caused by gravitational lensing of the CMB was first detected in 2013 by the SPT polarimeter (SPTpol) camera installed on the 10-meter South Pole Telescope (SPT), which is operated by an international scientific team (Figure 1). The SPT is co-located at the Amundsen-Scott South Pole Station with the BICEP2 (soon to be BICEP3) and Keck Array CMB experiments.



 South Pole Telescope at Amundsen-Scott South Pole Station.jpg


The South Pole Telescope at Amundsen-Scott South Pole Station



CMB radiation is the last echo of the immense energy burst that accompanied the Big Bang. Arno Penzias and Robert Wilson accidentally discovered it in 1964 as they experimented with cryogenic receivers to investigate sources of radio noise for Bell Telephone Laboratories in Holmdel, NJ. The CMB was the one noise source that the two scientists could not eliminate from their experimental data. Discovery of CMB radiation confirmed the cosmological Big Bang theory and earned Penzias and Wilson the Nobel Prize in Physics in 1978.


Based on the resolving power of that early-1960s experimental apparatus, the CMB appeared to be uniform in every direction and at all times of the day and night. That characteristic supported the theory that the CMB was a remnant of the Big Bang. More sensitive measurements, notably those performed by the Cosmic Background Explorer satellite, mapped the entire sky’s worth of CMB to a very high resolution and showed that there were minute variations (anisotropy) in the CMB, which further reinforced the theory that the CMB was a fingerprint of the Big Bang. This discovery earned George Smoot and John Mather the Nobel Prize in Physics in 2006.





Electrothermal equilibrium in superconductors and its ability to measure incident electromagnetic energy was discovered in the 1940s, but TES detectors only came into widespread use in the 1990s. They’re now widely employed for CMB experiments. The SPTpol camera’s helium-cooled, superconducting focal- plane microwave sensor is an array of 1,536 antenna-coupled TES bolometers paired as 768 polarization-sensitive pixels; 180 pixels are sensitive to 90-GHz microwave radiation and 588 pixels are sensitive to 150-GHz radiation.


The 150-GHz CMB sensor module consists of corrugated feedhorn-coupled TES bolometers fabricated at the National Institute of Standards and Technology (NIST) in Boulder, Colo. Each 150-GHz TES bolometer module contains a detector array with 84 dual-polarization pixels operated at a temperature of a few hundred milli-Kelvin. Incident microwave energy travels down a coplanar waveguide to a microstrip transition and that feeds a lossy gold meander (a heating resistor). The incident microwave energy flowing into the meander causes heating. The meander is thermally connected to the TES sensors, which are made of an aluminum manganese alloy. These TES devices operate in the middle of their superconducting transitions, so they are extremely sensitive to small changes in incoming optical power.


The 90-GHz CMB sensor modules consist of individually packaged, dual-polarization polarimeters that were developed at Argonne National Laboratory. Each 90-GHz pixel couples to the telescope through a machined, contoured feedhorn, which channels the CMB radiation to a resistive PdAu absorbing bar. The resistive absorbing bar is thermally coupled to a Mo/Au bilayer TES.



SPTpol Focal Plane Array small.jpg


The South Pole Telescope’s microwave focal-plane array. The inner seven hex-shaped modules are a 150-GHz array and the outer ring is a 90-GHz array. Every pixel has its own individual horn, which couples light to each pixel’s two TES bolometers.



For both the 150-GHz and 90-GHz sensors, thermal variations caused by microwave energy absorption create slowly varying changes in the resistance of each TES on the order of a few hertz. The resistance changes modulate a carrier current running through each of the 1,536 TES bolometers. These currents are then amplified by cryogenic superconducting quantum interference devices (SQUIDs). The need to bring all 1,536 measurements from the supercold environments of the focal-plane sensor and SQUID arrays to the relative warmth of the South Pole required the development of an innovative digital frequency-multiplexing (DFMUX) scheme implemented with Xilinx Virtex-4 FPGAs.


SQUIDs have high bandwidth, so a frequency-multiplexed arrangement is easily used in this application. This multiplexing scheme permits the sharing of SQUIDs and minimizes the number of wires crossing into the cryostat that cools the focal-plane sensor array without degrading each bolometer’s noise performance. The DFMUX was developed at McGill University in Montreal, one of the institutions operating the South Pole Telescope. The others include the University of Chicago; University of California, Berkeley; Case Western Reserve University; Harvard/Smithsonian Astrophysical Observatory; University of Colorado, Boulder; University of California, Davis; Ludwig Maximilian University of Munich, Germany; Argonne National Laboratory, and NIST.





The SPTpol camera uses a second-generation McGill DFMUX based on a Xilinx Virtex-4 FPGA. The FPGA digitally synthesizes a carrier comb that combines 12 carrier frequencies using direct digital synthesis (DDS). The carrier comb enters the focal-plane cryostat on a single wire and drives a set of 12 TES bolometers. Individual analog LC filters tune each of these 12 TES bolometers to a narrow frequency band. Each bolometer responds to the time-varying incident CMB radiation with a varying resistance over frequencies ranging from 0.1 Hz to 20 Hz. The varying resistance of the TES bolometer modulates the carrier current flowing through the bolometer. The 12 TES bolometer currents are then summed together to form a modulated “sky signal.”


A second DDS frequency comb called a “nuller” comb drives the summing node at the input to the SQUID amplifier. The nuller comb’s phase and amplitude are set to cancel the carrier comb through destructive interference, leaving just the signals detected by the bolometers plus a small residual amount of carrier power. One SQUID amplifies this signal, converts it to a voltage and passes it back to room-temperature electronics for filtering, A/D conversion and demodulation by the FPGA.




 BICEP2 FPGA-based Readout Module Small.png


Block diagram of a DFMUX-based TES bolometer system for measuring CMB radiation



The digital output of the ADC directly enters the Virtex-4 FPGA for demodulation. The demodulation scheme resembles the digital up- and downconversion (DUC, DDC) algorithms used for GSM mobile telephony, with some exceptions. First, the bandwidth for each TES bolometer channel is very narrow—on the order of tens of hertz. Second, the carrier combs are made from synthesized sinusoidal carriers generated by the Virtex-4 FPGA. Carrier modulation occurs within the TES bolometers in the cryostat.


One Virtex-4 FPGA operates four of the SPTpol camera’s 12-bolometer multiplex sets. The DFMUX design uses the Virtex-4 FPGA’s on-chip logic, memory and DSP facilities for digital frequency synthesis, demodulation (downconversion, filtering and decimation), time-stamping and buffering. Using one FPGA to generate both the carrier frequency comb and the nuller frequency comb, as well as to demodulate the sky signal, means that all signals operate in lockstep. It’s not possible for the comb generation and demodulation to drift relative to each other because they originate from the same master clock on the FPGA. Consequently, clock jitter is not a significant noise source, which measurements confirm.





There are two major blocks implemented within the FPGA: the digital multifrequency synthesizer (DMFS) and the digital multifrequency demodulator (DMFD). The system design uses two identical DMFS blocks for frequency synthesis. One generates the carrier frequency comb and the other generates the nulling signal. The frequency synthesizers operate at 200 MHz and employ 16-bit DACs running at 25 Msamples/second. The synthesizers are based on 11-bit, two’s-complement direct digital synthesizers created by the Xilinx DDS compiler. Per-channel frequency resolution is 0.006 Hz.


Demodulation of the sky signal starts with digital downconversion. The incoming signal is mixed with reference waveforms to produce individual baseband signals. The frequency and phase of the reference waveforms are independent of each other.


The demodulated sky signal has been sampled with 14-bit resolution at 25 Msamples/s but the bandwidth of interest is much smaller than the Nyquist bandwidth of this sample rate. Therefore, the demodulated baseband signals pass through cascaded integrator comb (CIC) decimation filters constructed from adders and accumulators in the FPGA. The first-stage CIC filter decimates the baseband signal by a factor of 128 using 28-bit precision. The output of this filter is then truncated to 17 bits.


The DFMUX time-domain-multiplexes eight bolometer channels (25 Msamples/s) into a CIC1 operating at 200 MHz. The CIC1 filter has an internal 28-bit data width and a 24-bit output. After CIC1 filtering, all bolometer channels are multiplexed together and feed a single CIC2, which has six variable decimation rates (by 16, 32, 64, 128, 256 and 512). The CIC2 filter is followed by a 152-tap FIR filter.


A channel identifier and time stamp are added to the FIR filter’s output and then sent to dual-ported buffer storage with a rotating buffer list. The SDRAM’s large buffer capacity eases latency requirements on the FPGA-based MicroBlaze soft processor, which runs Linux and supervises data flow through the system. Eased latency permits activation of the processor’s MMU and greatly improves Linux OS operation.


External control of the DFMUX board occurs over an Ethernet connection through an HTTP interface using two Web servers running on the MicroBlaze processor. All that’s needed to control the DFMUX board is a Web browser. A Python scripting environment provides direct access to board-level control registers for more detailed work such as instrument tuning.





The SPTpol camera is one of several such experiments looking at CMB radiation. The same DFMUX board used in the camera is also part of the EBEX balloon-borne “E and B Experiment” and the POLARBEAR CMB polarization experiment mounted on the Huan Tran Telescope at the James Ax Observatory in Chile. A more advanced version of the DFMUX board called the ICEboard, based on Xilinx Kintex-7 FPGAs, is just starting to deploy on new CMB experiments and in the Canadian Hydrogen Intensity Mapping Experiment (CHIME) radio telescope.


CHIME is a novel radio telescope located in a secluded valley near Penticton, British Columbia. The telescope consists of five large, 100 x 20-meter partial-cylinder reflectors roughly the size and shape of snowboarding half-pipes packed with arrays of radio receivers located along the focus of each partial cylinder. There are no moving parts (other than the Earth). When finished, CHIME will measure more than half of the sky each day as the Earth turns.


However, CHIME won’t be studying the CMB. It will be looking for evidence of dark energy by surveying 21-cm (400- to 800-MHz) radio emissions in a large 3D volume of space at distances ranging from 7 billion to 11 billion lightyears. CHIME will be measuring “baryon acoustic oscillations,” or BAOs, which are periodic density fluctuations in enormous cosmic structures consisting of hydrogen gas. BAO matter clustering provides cosmologists with a “standard ruler” of approximately 490 million light years, used for measuring immense distances. BAO signal variations could prove to be the signs of dark energy at work. At least, that’s the hope.


CHIME is essentially a phased-array radio telescope. It synthesizes an image by recording the electromagnetic signal across a stationary antenna array and then reconstructing the overhead sky from the data using 2D correlation and interferometry. CHIME will require 160 interconnected Kintex-7 FPGAs to process BAO signal data being received at several terabytes per second.





The inflation theory of cosmology posits that the universe underwent a violent expansion 10 to 35 seconds after the Big Bang—a physical expansion that exceeded the speed of light. That’s pretty hard to accept if you think that the speed of light is absolute, and most of us do. Part of that Big Bang theory suggests that inflation left behind a cosmic gravitational-wave background (CGB) in addition to the CMB, and that the CGB impressed a polarization signature  on the CMB. Results from the BICEP2 experiment are the first to confirm this theory.


Additional results from the SPTpol camera, EBEX, POLARBEAR, the Keck Array and the BICEP3 experiment are expected to reinforce that finding. For its part, CHIME will add yet another dimension to our quest for cosmological knowledge when it starts searching for dark energy.


Note: This article appears in the latest issue of Xcell Journal, the sister publication of Xcell Daily. It’s a longer version of a blog post that appeared previously in Xcell Daily. Click here for the latest issue of Xcell Journal. Read it online or download the PDF.



Further Reading


For more technical information about the SPTpol camera, TES bolometers and the FPGA-based DFMUX readout board, check out the following references:


J. E. Austermann, et al., “SPTpol: an instrument for CMB polarization measurements with the South Pole Telescope,” arXiv:1210.4970v1 [astro-ph.IM]


Ron Cowen, “Telescope captures view of gravitational waves,” Nature, March 17, 2014


Matt Dobbs, et al., “Digital Frequency Domain Multiplexer for mm-Wavelength Telescopes,” arXiv:0708.2762v1 [physics.ins-det]


M.A. Dobbs, et al., “Frequency multiplexed superconducting quantum interference device readout of large bolometer arrays for cosmic microwave background measurements,” arXiv:1112.4215v2 [astro-ph.IM]


J. W. Henning, et al., “Feedhorn-Coupled TES Polarimeter Camera Modules at 150 GHz for CMB Polarization Measurements with SPTpol,” arXiv:1210.4969v1 [astro-ph.IM]


J. T. Sayre, et al., “Design and characterization of 90-GHz feedhorn-coupled TES polarimeter pixels in the SPTpol camera,” arXiv:1210.4968v1 [astro-ph.IM]


Graeme Smecher, et al., “An Automatic Control Interface for Network-Accessible Embedded Instruments,” ACM SIGBED Review, Second Workshop on Embed With Linux (EWiLi 2012), Vol. 9 Issue 2, June 2012


Graeme Smecher, et al., “A Biasing and Demodulation System for Kilopixel TES Bolometer Arrays,” arXiv:1008.4587 [astro-ph.IM]


K. Story, et al., “South Pole Telescope Software Systems: Control, Monitoring, and Data Acquisition,” arXiv:1210.4966v1 [astro-ph.IM]


This very cool video demonstrates Jaguar’s “Virtual Windscreen,” an augmented reality tool for race drivers. The virtual windscreen, based on a heads-up display, shows you the best computed path to take on a race course, sets up slaloms with virtual traffic cones, and can show you racing against yourself using a ghost car to represent your best prior run. The video below demonstrates some of these new uses for Smarter Vision technologies in automotive applications.


Note: Putting this Jaguar video on Xcell Daily does not imply that Jaguar is using Xilinx products. It’s just a cool and very visual automotive demonstration of the Smarter Vision concept for Advanced Drivers Assistance Systems (ADAS).





Over the past weekend, the miniSpartan6+ Kickstarter FPGA dev board funded at nearly 11x the funding goal. There were 851 backers and $80,897 worth of pledges. The project blew past every stretch goal. If you are one of the 851 backers, I am sure the project members at Scarab Hardware appreciate your show of support—a lot.


The project had a $30 upgrade from a Xilinx Spartan-6 LX9 FPGA to a Spartan-6 LX25 FPGA. With that upgrade, you get significantly more processing power in the FPGA: 24,051 logic cells (instead of 9152), 936Kbits of block RAM (instead of 576), and 38 DSP slices (instead of 16). If you did not order the upgrade during the funding period, there’s a grace period thanks to Scarab. You have one week to upgrade your order to an LX25 using Scarab’s direct ordering page.


CASE STUDY: National Instruments Achieves New Efficiencies with Zynq SoC

by Xilinx Employee ‎07-15-2014 01:42 PM - edited ‎07-15-2014 01:47 PM (408 Views)

By Mike Santarini, Xcell Journal


National Instruments was an early adopter of the Zynq SoC and is already showing how leveraging the device as a platform can increase efficiencies and raise profitability. “What we are doing with the Zynq platform is creating our own platform,” said James Smith, director of embedded systems product marketing at NI (Austin, Texas). “We are a tools provider for scientists and engineers. We are creating a development platform that customers can design on top of.”


Xilinx and National Instruments have long worked closely together on Xilinx product road maps. This was especially the case as Xilinx was developing the Zynq SoC. NI was one of the first customers to receive shipments of the new device in November 2011 and has already put it to good use as a platform.


In the summer of 2013, NI announced not one but three new products based on the Zynq SoC: the high-end CompactRIO-9068 software-designed controller; a low-cost version targeted at students called myRIO; and another product called roboRIO for the First Robotics Competition.


Products, Profits Proliferate on Zynq SoC Platforms

by Xilinx Employee on ‎07-15-2014 11:17 AM (260 Views)

By Mike Santarini


Ever since Xilinx shipped the Zynq-7000 All Programmable SoC in late 2011, a bounty of products has been arriving. Today the Zynq SoC is at the heart of many of the world’s newest and most innovative automotive, medical and security vision products, as well as advanced motor-control systems that make factories safer, greener and more efficient. The Zynq SoC has also won sockets in next-generation wired and wireless communications infrastructure equipment as well as a wealth of emerging Internet of Things applications. By deploying a platform strategy leveraging the Zynq SoC and hardware/software reuse, they are able to quickly create many derivatives or variations of their products. The result is higher levels of design productivity and an improvement in the bottom line.


All Programmable Platforms: Foundation for Profitability

by Xilinx Employee on ‎07-14-2014 02:12 PM (269 Views)

By Mike Santarini, Publisher, Xcell Journal


When I first started covering the IC design industry as a trade journalist, the merchant ASIC market had already had its heyday and the custom digital IC business was rapidly turning to ASSP SoCs as a way to improve profit margins. Merchant ASICs came to dominance when differentiation of an end product’s performance and feature set relied mostly on its hardware—performance, power as well as unique functionality hardwired into the gates of a device. But the merchant ASIC business was short-lived.




Tom Hart, chairman and former CEO of Quicklogic, summarized it best at meeting we had years ago. “The key to making money in the semiconductor business is selling a lot of one type of chip to a lot of different customers,” said Hart. “The ASIC business is a crummy business. It is a bet on a bet. You have to bet that the customer you are building an ASIC for has built the right product for the right market.”



By the early 2000s, silicon process technology and gate counts had advanced to the point where companies could embed microprocessors and other IP into their custom digital designs, creating what quickly became known as systems-on-chip. These SoCs allowed semiconductor companies to build a single device and sell it to a broader number of customers—a business we call today merchant ASSPs. With ASSPs, the on-chip hardware typically meets a minimum hardware requirement and any and all customer differentiation occurs in software. While still popular, the ASSP business model also has flaws—but mainly for the customer.


The biggest problem is that semiconductor vendors generally do not build an off-the-shelf ASSP until standards are nailed down and a market is already established. So if you as a customer want to be first to market, get the highest product ASP and maximize profitability, you still need to create custom hardware as well as software for your own differentiated chips. Further, to maximize the time you dominate the market and maintain your first-to-market price point, you need end-product differentiation. This fact points to yet another flaw in the off-the-shelf ASSP model: If you can buy it from a vendor, someone else can too. Arguably, it is relatively easy and fast to differentiate the software functionality once your ASSP is available. But it is also relatively easy for your competitors to create lower-cost knockoffs of your design or even improve it using the exact same hardware. As such, ASSPs have proven great for companies that want to build “me-too” products and get the leftovers of a given market opportunity’s carcass before it is completely picked clean.


In the face of daunting silicon costs, many companies are turning to a platform business model to maximize profitability. That is, you create a first, custom chip at a given silicon process node and then build less-expensive derivatives leveraging IP and design reuse. Companies can build platforms with ASICs, their own ASSPs or merchant ASSPs, but those options are still weighed down by issues I pointed out above. So a growing number of customers are taking the next step in the semiconductor evolution and building platforms with Xilinx’s award-winning Zynq-7000 All Programmable SoC. As you will read in the cover story (Xcell Journal, Issue 88), the Zynq SoC is by far the wisest business as well technological choice available today for building a differentiated product platform and maximizing bottom-line profitability.


Note: This editorial by Mike Santarini appears in the latest issue of Xcell Journal, the sister publication of Xcell Daily. It’s such an outstanding analysis that I wanted to make sure that Xcell Daily readers saw it too. Click here for the latest issue of Xcell Journal. Read it online or download the PDF.

Issue 88 of Xcell Journal now available

by Xilinx Employee on ‎07-14-2014 10:43 AM (402 Views)

Xcell Journal Issue 88.jpgYou’ve been waiting and now you can get issue 88 of Xcell Journal. Read it online or download the PDF.


Cover story: Products, Profits Proliferate on Zynq SoC Platforms


Other articles in this issue:


  • The Search for Gravity Waves and Dark Energy Gets Help from FPGAs
  • Virtex UltraScale FPGA Enables Terabit Systems
  • Goodbye DDR, Hello Serial Memory
  • Design Reliability: MTBF Is Just the Beginning
  • Protocol-Processing Systems Thrive with Vivado HLS
  • In FPGA Design, Timing Is Everything
  • NI System-on-Module Brings Innovative Products to Market Fast


Plus the latest updates you have come to expect.




Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

by Xilinx Employee ‎07-14-2014 10:03 AM - edited ‎07-14-2014 01:03 PM (771 Views)

By Adam Taylor


Having looked at the different types of a real time operating system in my previous blog post (see “Adam Taylor’s MicroZed Chronicles Part 40: MicroZed Operating Systems Part Two”), I think it is a good idea to look at how tasks communicate, how they share available hardware resources, and the potential pitfalls.


When two or more tasks want to share a resource— the Zynq SoC’s XADC for example—it is possible that the tasks might request the resource at the same time. Resource access needs to be controlled to prevent contention and this is one of the operating system’s most important duties. Without the correct resource management, deadlock or starvation might occur.


Amelia Dalton over at EEJournal interviewed Jim Beneke, Avnet’s VP of Global Marketing, about the upcoming X-Fest event series taking place in about 40 cities around the globe. If you’re sitting on the fence about attending, then maybe Jim and Amelia can help you make the right decision—which of course it to avail yourself of this free, convenient technical training for an extra boost against the competition.


Here’s the podcast. The X-Fest interview takes place in the first five minutes. (Note: the Podcast is silent for the first 10 seconds.):





X-Fest training courses include:


Design Essentials


  • Power and thermal Design
  • UltraScale Memory Interfaces
  • Zynq-7000 All Programmable SoC Boot and Configuration Procedures
  • Zynq-7000 All Programmable SoC Modules


Techniques & Applications


  • High-Speed Digital Signal Processing in UltraScale FPGAs
  • Partial Reconfiguration in Zynq-7000 All Programmable SoCs
  • Using Operating Systems with Zynq-7000 All Programmable SoCs
  • Zynq-7000 All Programmable SoCs for Intelligent Drives


Zynq All Programmable SoCs and the IoT (Internet of Things)


  • Adding Smarter Vision to your Product with Zynq-7000 All Programmable SoCs
  • Adding Wireless Connectivity to Zynq-7000 All Programmable SoC Systems
  • Building Blocks for Enhancing User Interfaces
  • Making the IoT Smarter



Register here.



X-fest logo.png

I’ve just received word that Scarab Hardware has decided to upgrade the miniSpartan6+ FPGA dev board to the Xilinx Spartan-6 LX9 FPGA in a BGA256 package even if the Kickstarter funding period ends before reaching the $65K stretch goal. As of this writing, pledges for the project are at $58,415 (7.8x over goal) with three days left in the funding period. With the package change, Scarab Hardware has also added a $30 option that replaces the Spartan-6 LX9 FPGA with a pin-compatible Spartan-6 LX25 FPGA—with greatly expanded on-chip resources including 24,051 logic cells (instead of 9152), 936Kbits of block RAM (instead of 576), and 38 DSP slices (instead of 16). So you get significantly more processing power to play with for the $30 upgrade.



miniSpartan6+ 3D model.png



TCP and UDP Session Hardware Accelerator supports 16K concurrent sessions on VC707 dev board

by Xilinx Employee ‎07-10-2014 11:06 AM - edited ‎07-10-2014 11:11 AM (475 Views)

Intilop has ported its 10G TCP and UDP Offload Engine (TOE/UOE) to the VC707 dev board based on a Xilinx Virtex-7 XC7VX485T FPGA. The Intilop TOE/UOE implemented with an FPGA supports as many as 16K simultaneous TCP and UDP connections and unlimited continuous connections on 10G Ethernet ports with ultra-low latency (sub 100nsec) and zero jitter regardless of the number of connections. The entire TOE/UOE subsystem consumes fewer than 12K slices and 4Mbytes of BRAM. Integration of the pretested Intilop TOE/UOE on an FPGA-based eval board permits immediate experimentation and customization for specific networking applications.



 Intelop TOE UOE on Xilinx VC707 Eval Board.jpg

HMC demo shows 15Gbps operation per link at last month’s International Supercomputer Conference

by Xilinx Employee ‎07-09-2014 02:50 PM - edited ‎07-09-2014 02:52 PM (728 Views)

Xilinx, Pico Computing, and Micron demonstrated a working HMC (Hybrid Memory Cube) demo last month at the International supercomputing Conference held in Leipzig, Germany last month. The demo showed a Xilinx Kintex UltraScale All Programmable device operating a Micron HMC at 15Gbps/pin using a controller IP core from Pico Computing. The demo shows 8 links (half of a full HMC lane) operating.


Synopsys introduced the new ProtoCompiler for its HAPS FPGA-based prototyping systems—used for ASIC prototyping—back in April. HAPS-70 Series and HAPS-Developer eXpress Series systems are based on Xilinx Virtex-7 All Programmable devices.



Synopsys HAPS Systems.jpg


Synopsys’ ProtoCompiler promises:


  • Decreased runtime from hours to minutes for up to 250 million ASIC gate designs
  • Automated design partitioning across multiple FPGAs (supported by some HAPS systems)
  • 2X faster prototype performance on average
  • Captures seconds of trace data with gigabytes of storage capacity for superior debug visibility


Now you can learn more about the Synopsys ProtoCompiler through a free Webinar on July 23. Register here.

You can bond two FPGAs or even two FPGA boards together and get them to act as one device using parallel or serial I/O and a combination of Chip2Chip LogiCORE and AXI IP, as demonstrated in the new Application Note “AXI Chip2Chip Reference Design for Real-Time Video Application” (XAPP1160). This particular application note focuses on transporting real-time HD video streams between two Kintex-7 FPGA KC705 Eval Boards or between a Kintex-7 FPGA KC705 Eval Board and a Zynq-7000 AP SoC ZC706 Eval Board, interconnected by their FMC HPC connectors.


The basic idea here is that the instantiated IP in the FPGA or SoC and the FMC-to-FMC cabling “disappears” and other logic on one All Programmable device thinks it’s talking to a conventional AXI port while the transmitted and received data is actually traveling a fair distance as it makes its way across the connecting cable and “appears” on the AXI port on the other board’s All Programmable device. Consider it AXI teleportation.


Character display overlay on Zynq-based ZYBO video output. A work in progress

by Xilinx Employee ‎07-08-2014 10:28 AM - edited ‎07-08-2014 10:28 AM (332 Views)

Brian Swetland, a software engineer at Google, posted an interesting discussion on Google+ about his work with the Zynq-based Digilent ZYBO dev board on July 4.  He’s experimenting with video frame buffers and character display overlays. He writes “All of this is a work in progress with plenty of rough edges and some hacky bits in places, but it's at a point where it's doing some mildly interesting stuff, so I figured I'd share.”


Here’s a photo of his current output:



Brian Swetland Video Overlay on Digilent ZYBO.jpg 



The Roger Lanctot at the Embedded Vision Alliance Meeting May 2014.jpgEmbedded Vision Alliance has posted a free video of Roger Lanctot’s presentation on ADAS (Automated Driver Assist Systems) at the May Embedded Vision Alliance member meeting. Lanctot is the Associate Director of the Automotive Practice at Strategy Analytics. Automotive applications are the fastest growing market for Smarter Vision technology and Lanctot’s excellent presentation gives you a fast background in the current state of worldwide ADAS rollout.


Automobile accidents are currently killing 1.25 million people per year worldwide and that figure is rising. It will soon reach 2 million people per year. A chilling statistic. Consumer surveys show that people want safety features in cars, that these safety features sell cars, and that interest in ADAS features is actually higher than for any other electronics-based automotive category. Consumers want these ADAS safety features even more than infotainment accessories, which fall well down the list of desired features, says Lanctot.


There are six days left in the miniSpartan6+ FPGA board Kickstarter funding period. (See “MiniSpartan6+ FPGA board on Kickstarter: 4.5x over funding goal with 25 days left” and “Credit-card sized miniSpartan6+ FPGA development board on Kickstarter sold out, unless…”) The project is currently 6.9x over its $7500 funding goal thanks to pledges from 642 backers, so it will be funded next Sunday no matter what. Meanwhile the project’s initiator, Scarab Hardware, has set a new stretch goal of $65,000. If the project’s pledges hit that goal, Scarab will be upgrading the board’s Xilinx Spartan-6 LX9 FPGA from a TQFP144 package to an FBGA256 package. So what? The change increases the available I/O pins and makes the board that much more useful for prototyping.


Adam Taylor’s MicroZed Chronicles Part 40: MicroZed Operating Systems Part Two

by Xilinx Employee ‎07-07-2014 10:30 AM - edited ‎07-07-2014 12:08 PM (620 Views)

By Adam Taylor



Having introduced the operating systems I intend to demonstrate on the Zynq SoC, the first OS I intend to implement on the MicroZed is the Micrium uC/OSiii, which is a hard real-time operating system available for download here.


This OS has been used on number of very interesting systems and is currently in process for MISRA-C, DO178B level A, SIL3/4, and IEC61508 certification. Consequently, it should have a wide appeal to many designers using the Zynq SoC.


I chose Micrium’s uC/OSiii for my first OS example because I am most interested in using the Zynq SoC for industrial, military, aerospace, and other applications with challenging environments. I think the Zynq SoC’s benefits are really apparent in these application areas. They best demonstrate the SWAP-C (Size, Weight, and Power-Cost) and the performance benefits of a Zynq SoC implementation versus all other alternatives.


However, before I jump off and start discussing OS implementation, I thought I would provide a little back ground information on real-time operating systems (RTOSes).


Less than a month ago, EVT RazerCam.jpga blog post in Xcell Daily discussed the new RazerCam smart industrial camera announced by EVT. (See “New Zynq-based RazerCam is one smart industrial machine vision camera with three different sensor options.”) That post discussed the Linux operating system running on the RazerCam’s integrated Xilinx Zynq SoC and mentioned the ability to program the camera’s two integrated ARM Cortex-A9 MPCore processors on the Zynq SoC with local-processing algorithms using C or C++. EVT has just introduced a revision to its EyeVision 3.0 software that integrates graphical FPGA programming software from Silicon Software, which adds the ability to greatly accelerate image processing using the Zynq SoC’s on-chip programmable logic.



One UG578 UltraScale GTY Transceivers.pngof the many distinguishing features of Xilinx Virtex UltraScale All Programmable devices is the availability of twenty to sixty configurable, 32.75Gbps GTY bidirectional serial transceivers. Here are some of the commonly used high-speed serial interface standards that can use these transceivers:




  • PCIe, Rev 1.1/2.0/3.0
  • SFP+ (SFF-8431)
  • 10GBASE-R/KR
  • Interlaken
  • XAUI (10Gbps attachment unit interfaceI)
  • RXAUI (reduced pin extended attachment unit interface)
  • CAUI (100Gbps attachment unit interface)
  • XLAUI (40 Gb attachment unit interface)
  • CPRI (Common Packet Radio Interface)
  • OBSAI (Open Base Station Architecture Initiative)
  • OC-48/192
  • OTU-1, OTU-2, OTU-3, OTU-4 (Optical channel Transport Unit)
  • SRIO (Serial RapidIO)
  • SATA (Serial Advanced Technology Attachment)
  • SAS (Serial attached SCSI)
  • SDI (Serial Digital Interface)


Achieving such broad I/O standard coverage requires a significant amount of flexibility so the following enhancements have been added to these high-speed UltraScale SerDes ports:


  • Increased line rate support up to 32.75Gbps
  • Enhanced 64B/66B and 64B/67B gearbox support
  • Improved PRBS generator and checker
  • Additional datapath to support PCIe Gen3
  • Enhanced clocking to provide additional flexibility in supporting 64B/66B type protocols in the interconnect logic


For more details on the UltraScale GTY transceivers, see “UltraScale Architecture GTY Transceivers” (UG578).


If you’re considering DDR4 SDRAM for your next design, there’s a brand new White Paper you should read titled “High-Performance, Lower-Power Memory Interfaces with UltraScale Architecture FPGAs” (WP454). Many next-generation systems will need the additional bandwidth of DDR4 SDRAM, the lower operating power of such systems, or both to meet system-level objectives. DDR4 SDRAM is an evolutionary step beyond DDR3 SDRAM, but there are many changes required to both the memory controller and to the memory PHY when moving from DDR3 to DDR4. The new Xilinx WP454 White Paper walks you through these changes to help you successfully extract the additional performance from DDR4 memory.


Here’s a block diagram of the configurable UltraScale DDR4 memory controller and PHY, which the Vivado MIG (Memory Interface Generator) can create:


 UltraScale DDR4 Memory Controller and PHY Block Diagram.png


About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, embedded systems design, design IP, EDA, and programmable logic.