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Adapteva celebrates shipping 10,000 Zynq-based Parallella parallel computing supercomputing dev boards

by Xilinx Employee ‎09-22-2014 02:06 PM - edited ‎09-22-2014 06:38 PM (145 Views)

Adapteva’s open-source Parallella supercomputing development board based on the Xilinx Zynq SoC, was a Kickstarter project that raised $898,921 in late 2012. Adapteva says it has now shipped more than 10,000 boards. Applications for this board include:

 

  • Parallel computing (programming, teaching, methods)
  • HPC (high-performance computing) applications
  • SDR (software-defined radio)
  • Robotics/Drones/Computer Vision
  • Artificial Intelligence
  • FPGA Research

 

 

The Parallella board includes a Zynq Z7010 SoC and an Adapteva Epiphany multicore processor chip with 16 parallel computing cores.

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Next week is ARM TechCon in Santa Clara, California. If you’re using ARM processors, you need to be there. If you’re using or thinking about using the ARM-based Zynq All Programmable SoC from Xilinx, I’ll be doing two Zynq-based product teardowns on the expo floor on October 2 in the morning at 11:30am. (See “Teardown Thursday @ ARM TechCon: What’s In There Besides Zynq?”)

 

According to a Google+ posting by UBM, you can get a free ARM TechCon expo pass by using the special registration code GPFLASHEXPO1 — but only for the next 48 hours so you’d best hurry. At this point, that represents a $59 savings. Register here.

New Webinar: How to Optimize Your SerDes Design During the Pre-layout Phase

by Xilinx Employee ‎09-22-2014 10:01 AM - edited ‎09-22-2014 10:05 AM (88 Views)

High-speed SerDes ports operating at multi-GHz speeds is one of the best connectivity tools in the system designer’s toolbox. You need some training to use this tool effectively and Keysight Technologies (the company formerly known as Agilent) is going to help you sharpen your SerDes saw with a free hour-long Webcast on September 25. The Webinar is titled “How to Optimize Your SerDes Design During the Pre-layout Phase” and it starts at 10am Pacific Time in the US.

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By Adam Taylor

 

In my last blog we had looked at the Zynq SoC’s OCM (On-Chip Memory) for inter-processor communications in an AMP environment. Now let’s write come code and use this facility.

 

The demo for this will use CPU0 to communicate over the UART link to a laptop. We’ll send an 8-bit ASCII value from the laptop to the Zynq Soc’s UART. Once received, this 8-bit value will be transferred into the selected OCM memory address, which is shared between the two processors. Each time its private timer expires, CPU1 will read this memory address and set its GPIO output pins accordingly. LED’s on the MicroZed I/O Carrier Card connected to these Zynq SoC pins through the inter-board headers will display the received ASCII pattern. We’ll be able to visually confirm that the correct value has been passed between the CPUs from the display on the LED.

 

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JESD204B ADC interface magically commutates Gsamples/sec into a polyphase channelizer

by Xilinx Employee ‎09-18-2014 04:53 PM - edited ‎09-18-2014 07:33 PM (359 Views)

Here’s a neat trick I learned last week at X-fest in San Jose from Luc Langlois, Director of Global Technical Marketing and Digital Signal Processing at Avnet Electronics. The way to get FPGAs to perform direct conversion and processing on multi-GHz RF signals is to take the multi-GHz sample stream from the high-speed ADC and feed it into a polyphase channelizer to parallelize the processing.

 

You need math to understand this—math involving the equivalence theorem (heterodyne + baseband filter = bandpass filter + heterodyne) and the Noble Identity. Math that’s way beyond me so I’m not going to attempt an explanation here because I’ll just get it wrong.

 

However, I’m going to get the system-design part right, which is what you need to know after the math proves it’s OK for you to do it.

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Small Cell Backhaul Solutions: Which Technology Fits the Bill?

by Xilinx Employee ‎09-18-2014 03:51 PM - edited ‎09-18-2014 03:51 PM (194 Views)

Did you miss the live Xilinx Webinar on Small Cell Backhaul Solutions? Nope, you didn’t because it’s on September 30. This free webinar discussed wireless backhaul capacity, networking, and signal processing challenges for small-cells. It then focuses on the technologies -- millimeter-wave (E and V bands) radio technology in particular, as well as hardware and software design solutions leveraging Xilinx All Programmable SoC platforms. Examples will be given showing how PHY and L2-L3 functions can be implemented in a flexible, low-risk, and cost-efficient manner.

 

Register here.

For a quick overview of ways to add interactivity to digital signage with vision algorithms, take a look at “Practical Computer Vision Enables Digital Signage with Audience Perception,” a new article on the Society for Information Display’s Web site. The article discusses interactive vision algorithms including person discernment, face detection and analysis, and gesture recognition. This article is a joint project led by Brian Dipert from the Embedded Vision Alliance with Rabindra Guha and Tom Wilson from CogniVue, and Robert Green from Xilinx.

 

 

A complete course in FPGA-based product planning from Pentek—in a 50-minute video

by Xilinx Employee ‎09-18-2014 11:11 AM - edited ‎09-18-2014 11:14 AM (224 Views)

Pentek designs rugged, high-speed, real-time recording systems and embedded boards for DSP, SDR (software-defined radio), and data acquisition. The company introduced its Cobalt series of PCIe DSP boards based on Xilinx Virtex-6 FPGAs in 2009. When Xilinx 7 series FPGAs became available, Pentek added the Onyx board series to its product line. The Onyx boards are based on Virtex-7 FPGAs and they accept the analog and digital I/O boards originally designed for the Cobalt series.

 

Why tell you all of this? Because Pentek has developed multi-generational and multi-product-line perspectives with respect to FPGA-based product planning and development. Amazingly, the company just posted a 50-minute video, “Latest Design Strategies using Xilinx Virtex 7 FPGA for Software Radio,” on YouTube that walks you through the thought processes for developing such multi-generational product lines. Although the point of this video is using Pentek boards and Xilinx FPGAs for SDR, the first half of this video is filled with general design information and some great ideas that apply to most—if not all—products based on programmable logic.

 

Worth watching, even if SDR isn’t your thing.

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Avnet X-fest Asia events now open for registration. Events in November through December

by Xilinx Employee ‎09-18-2014 09:39 AM - edited ‎09-18-2014 09:40 AM (173 Views)

X-fest logo.png

 

Avnet has opened registration for the X-fest sites in Asia:

 

  • Beijing, Tuesday, November 04, 2014
  • Xian, Thursday, November 06, 2014
  • Sydney, Friday, November 07, 2014
  • Singapore, Tuesday, November 11, 2014
  • Shanghai, Thursday, November 13, 2014
  • Shenzhen, Tuesday, November 18, 2014
  • Seoul, Thursday, November 20, 2014
  • GuangZhou, Thursday, November 20, 2014
  • Chengdu, Tuesday, November 25, 2014
  • Shenyang, Thursday, November 27, 2014
  • Nanjing, Tuesday, December 02, 2014
  • Hsinchu, Thursday, December 04, 2014
  • Bangalore, Tuesday, December 09, 2014
  • Taipei, Thursday, December 11, 2014
  • Hangzhou, Tuesday, December 16, 2014

 

X-fest is a mix of product demonstrations and technical seminars. If you’re interested in learning about the use of Xilinx All Programmable FPGAs and Zynq SoCs, I can recommend these day-long events. I feel confident in telling you that it will be time well spent.

 

Register here

 

If you happen to be in Cannes next week for ECOC 2014, you’ll be able to see several 100Gbps demos built upon Xilinx UltraScale FPGAs sending and receiving data over multiple 25.78Gbps electrical connections:

 

  • 25.78G Molex Backplane Demonstration
  • 25.78G TE Connectivity STRADA Whisper Connector and Backplane and Semtech Retimer Interoperation Demonstration
  • Interoperation with Finisar optical CFP4 ER4f 100Gbps prototype driving 40km of single-mode fiber
  • Demo of the industry's first single-chip 400GbE solution, implemented in a Xilinx Virtex UltraScale VU095 FPGA, driving four sets of Sumitomo Electric CFP4 LR4 modules.

 

You can see a video of that last demo right now. Click here.

Judges for the Elektra European Electronics Industry Awards 2014 just announced finalists in 16 product categories and have named the Xilinx UltraScale FPGA as a finalist in the Digital Semiconductor Product of the Year category.

 

Note: The UltraScale FPGA is the only programmable logic semiconductor device named as a finalist.

 

Details here.

It’s late 2014. Do you know where your SDRAM is? Where it will be?

by Xilinx Employee ‎09-17-2014 01:49 PM - edited ‎09-17-2014 02:36 PM (350 Views)

Last week at X-fest San Jose, I attended four technical sessions and the first was about memory interfaces and FPGAs—specifically Xilinx UltraScale FPGAs. The session had a lot of valuable general material about SDRAM in it. Bryan Fletcher, a Technical Marketing Director at Avnet, started by talking about the market dynamic between DDR3 and DDR4 SDRAM. DDR3 SDRAM is currently the volume leader, which means the cost/bit is lower for DDR3 memory than for other SDRAM generations.

 

That’s not going to last.

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Join National Instruments (NI), Cloudium, and Xilinx as we tear open the Zynq-based NI VirtualBench All-in-One Benchtop Instrument (mixed-signal oscilloscope, function generator, logic analyzer, DMM, programmable dc power supply, and digital I/O control lines) and the Cloudium Systems Integrated Media Processing Platform (a cloud-centric, fanless, multimedia thin client). We’ll discuss how these products are designed and built—from an engineer’s perspective—during a mid-day Teardown Thursday session at ARM TechCon in Santa Clara, California. It’s all happening on Thursday, October 2nd starting at 11:30 am in the Main ARM TechCon Theater on the exhibit floor.

 

 

NI Virtual Bench Photo.jpg

 

The NI VirtualBench All-in-One Benchtop Instrument

 

 

 

Haven’t registered for ARM TechCon yet? Better fix that now. Click here.

Totem FPGA-based Virtual Reality Goggles: The Kickstarter Video

by Xilinx Employee ‎09-17-2014 09:53 AM - edited ‎09-17-2014 09:55 AM (288 Views)

Yesterday, I published a blog about the Totem Virtual Reality headset, a Kickstarter project initiated by Vrvana. Totem uses a Xilinx 7 series FPGA for video processing, which involves 3D processing based on inputs from the headset’s HDMI input, a pair of stereo cameras, and an integrated accelerometer. It’s designed to work with:

 

  • OSX
  • Windows
  • Linux
  • Playstation 3, 4
  • Xbox One, 360
  • iOS
  • Android

 

 

The project funding level as of yesterday was just over $70,000. Today, it’s a Kickstarter Staff Pick and the pledge level has jumped above $100,000.

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FPGA-based Virtual Reality Goggles appear as a Kickstarter project—with 4 weeks left to fund!

by Xilinx Employee ‎09-16-2014 05:26 PM - edited ‎09-16-2014 06:32 PM (790 Views)

Vrvana’s Totem premium VR (Virtual Reality) headset plugs into an HDMI video source and plunges you into the world of 3D—and yes, the real-time video processing is done on a Xilinx 7 series FPGA. What makes the Totem headset merit the adjective “premium”? Could be the “no-compromise, full-HD-resolution 1080p OLED display” and the accompanying wide field of view. Could be the on-board stereo camera pair and the build-in accelerometer. Could be the immersive binaural sound generation that maintains the illusion of spatial reality. Could be all of those things plus a few more.

 

 

 

Vrvana Totem VR Headset.jpg

 

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Rapid prototyping FMC module has dual 14-bit, 1GSPS ADC and 16-bit, 2.8 GSPS DAC with JESD204B

by Xilinx Employee ‎09-16-2014 04:58 PM - edited ‎09-17-2014 05:50 AM (345 Views)

The AD-FMCDAQ2-EBZ rapid prototyping FMC module from Analog Devices contains the company’s AD9680 dual 14-bit, 1 Gsamples/sec ADC and the AD9144 quad 16-bit, 2 Gsamples/sec DAC (with two ADC and two DAC channels brought out to coaxial connectors), an AD9523 clock, and power management components. The module is supported by MathWorks development tools and Xilinx FPGA development kits.

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(0 Views)

 

Last week at X-fest San Jose, I found out that Avnet and seven of its power semiconductor partners have developed a standard form factor power supply module called Mini-Module Plus Power Modules for Avnet’s Zynq SoC Mini-ITX board and other development boards based on Xilinx 7 series devices. The really interesting thing about this power module form factor is that there are eight different versions depending on which power supply vendor you prefer.

 

The seven power semiconductor vendors are:

 

  • Analog Devices
  • GE Critical Power
  • Maxim
  • Panasonic
  • Rohm
  • STMicroelectronics
  • Texas Instruments (two reference designs)
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Single-chip 400G Ethernet demo based on UltraScale FPGA “works like a charm” on 4-minute video

by Xilinx Employee ‎09-16-2014 06:58 AM - edited ‎09-17-2014 05:03 PM (521 Views)

This 4-minute video demo of the industry’s first single-chip solution for 400G applications based on one 20nm Virtex UltraScale VU095 device on a VCU109 development board; four Sumitomo Electric CFP4 optical modules driven by 16 GTY SerDes ports on the UltraScale FPGA, each running at 25.78Gbps; and 10 km of optical fiber. The demo “works like a charm,” as Martin Gilpatric says in the video. It’s clear that this demo is live because transmission stops immediately when Gilpatric pulls one of the four fibers from its socket. By the way, transmissions are error-free until Gilpatric pulls the plug.

 

This demo also employs Xilinx Ethernet MAC and PCS IP specifically developed for 400G. Because 400G Ethernet is in the pre-standard phase, putting these IP components into programmable logic allows designers to experiment with 400G designs while tracking any changes to the spec as 400G Ethernet develops into a formal standard.

 

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Open Source AXIOM Beta 4K Digital Cinema Camera based on Zynq SoC and MicroZed now on IndieGoGo

by Xilinx Employee ‎09-15-2014 05:14 PM - edited ‎09-15-2014 06:31 PM (708 Views)

AXIOM Beta will be the first 4K digital cinema camera to be based on free software and open hardware. At its heart beats a Xilinx Zynq SoC, which combines two ARM Cortex-A9 MPCore processors and Xilinx 7 series programmable logic. The programmable logic performs all of the camera’s image processing in real time. You can now help to fund this amazing open-source undertaking through an IndieGoGo project. Funding ends in three weeks.

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Avnet Zynq SoC Mini-ITX demo uses partial reconfiguration for SDR (Software-Defined Radio) application

by Xilinx Employee ‎09-15-2014 11:07 AM - edited ‎09-17-2014 02:23 PM (851 Views)

Here’s a quick 4-minute video where Avnet Technical Marketing Engineer Tom Curran demonstrates an SDR (software-defined radio) application running on a Zynq SoC installed on an Avnet Zynq Mini-ITX development board. This demo from last week’s Avnet X-fest in San Jose uses the Analog Devices AD9361 high-performance, highly integrated RF Agile Transceiver chip and shows the Zynq SoC’s partial-reconfiguration capability. In addition, there’s a short segment at the end of this video with a discussion of AMP (asymmetric multiprocessing), a different demo that can run on the Zynq SoC and the Mini-ATX board.

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Zynq SoC and Sensor Fusion demo, live from X-fest San Jose

by Xilinx Employee on ‎09-15-2014 10:40 AM (293 Views)

Global Technical Marketing Engineer Dan Rozwood demonstrated his Zynq-based sensor fusion demo at last week’s one-day Avnet X-fest held in San Jose. The demo was inspired by the sort of sensing needed for an industrial plastics extruder. It combines data from at least nine sensor types:

 

  1. Analog and digital isolated inputs
  2. Remote current sensing
  3. RTD temperature sensor
  4. Ambient pressure transducer
  5. Quad thermocouple sensor
  6. Accelerometer to sense motor movements and bearing health
  7. Voltage monitor and power-consumption sensor
  8. MR (magneto resistive) sensor for monitoring motor movement
  9. Inductive sensor for monitoring motor movement

 

All of these sensors connect to appropriate interfaces in the Zynq SoC, which provides true parallel processing to ensure the time correlation among the sensor readings. As Rozwood says in the 8-minute video below, sensor fusion is about “putting three things in and getting four out.” By that, he means that the various sensor inputs can be combined to derive other measurements from the sensed parameters.

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By Adam Taylor

 

 

Last week, we got AMP (asymmetric multiprocessing) up and running on the Zynq SoC and looked at the basic software running on the Zynq SoC’s two ARM Cortex-A9 MPCore processors. I now want to explore how we can use the Zynq SoC’s OCM (On-Chip Memory) to communicate between the cores. In the previous 48 instalments of the MicroZed Chronicles, we have not discussed the OCM except in passing. As we plan to use the OCM going forward, we need to understand more about what it is and how it functions. Like most things on the Zynq SoC, the OCM is much more powerful than its simple name suggests.

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I had to write about this cool little Zynq-based robotic instrument controller I saw at X-fest San Jose yesterday. It’s a project by Dr. Lawrence West, president of Swift Control Systems here in Silicon Valley, who I met by pure chance. By eyeball estimation, the circular controller board measures a mere three inches or so in diameter. It sports a variety of analog and digital sensor inputs and communications ports. This board is designed to control a dual-gimbal mirror assembly on an optical table. The idea is for the components on the optical table to be able to talk to each other, making mirror and optics alignments much easier and saving hours of setup time. Cool idea.

 

I plunked the board on a nearby table to shoot some images. Here’s a photo of the top of the board:

 

 

Zynq-based Robot Controller Top.jpg

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PicoZed: Another clever Zynq-based SOM from Avnet

by Xilinx Employee ‎09-12-2014 02:51 PM - edited ‎09-15-2014 08:36 AM (1,190 Views)

Now available for order: the PicoZed SOM (system on module) from Avnet, based on the Xilinx Zynq All Programmable SoC. A PicoZed was on display yesterday at X-fest San Jose. Here’s a quick snap of the PicoZed and its I/O Carrier card from the event:

 

PicoZed at X-fest San Jose 2014.jpg

 

 

The PicoZed board comes in four flavors:

 

  • Zynq 7010-based PicoZed, $179 (each, in quantities of 100)
  • Zynq 7020-based PicoZed, $229 (each, in quantities of 100)

PicoZed boards with high-speed SerDes transceivers:

 

  • Zynq 7015-based PicoZed, $299 (each, in quantities of 100)
  • Zynq 7030-based PicoZed, $399 (each, in quantities of 100)

 

The I/O Carrier Card is $425 in unit quantities.

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I just spent the day at Avnet’s San Jose X-fest featuring many technical talks about using Xilinx All Programmable FPGAs and the Zynq SoC. These seminars were packed with usable content and the day is free (including lunch). If you’re in the Boston vicinity, be sure to sign up for next week’s event on September 17. Click here for the entire North American X-fest schedule.

 

I’ll be blogging about what I learned today over the next week or so. Stay tuned.

 

S2C’s TAI Player Pro is a GUI-based tool that partitions large logic designs across multiple FPGAs and then maps these designs to the company’s TAI Logic Modules based on Xilinx Virtex-7 2000T 3D FPGAs. The latest version of TAI Player Pro, version 5.1, automatically inserts LVDS pin multiplexing among the FPGAs to improve emulation performance. After mapping the design to the TAI Logic Module, the TAI Player Pro GUI monitors and controls the running prototype. The tool handles single-board TAI Logic Module configurations with 1, 2, and 4 FPGAs per module and can also map and route designs across multiple TAI Logic Modules.

 

One of S2C’s QuadE V7 TAI Logic Modules can pack system designs as large as 80M ASIC gates into its four on-board Xilinx Vitex-7 2000T FPGAs. You can populate the module’s four on-board DDR3 SO-DIMM sockets with as much as 32GB of DDR3 memory. The QuadE V7 TAI Logic Module supports 48 channels of high-speed 10Gbps transceivers. You can use these transceivers to implement a variety of high-speed interfaces including PCIe, SATA, and XAUI. A USB2.0 port serves as a download port for FPGA configurations and the new QuadE V7 TAI Logic Module also supports runtime features through an Ethernet connection to permit remote operation via the Internet or other IP networks. Here’s a block diagram of the S2C QuadE V7 TAI Logic Module:

 

 

 S2C QuadE V7 TAI Logic Module Block Diagram.jpg

 

 

S2C reports that one of its customers has already used these tools to partition a 300M-gate design over 24 FPGAs.

 

3D Plus module puts Spartan-6 FPGA, mobile DDR SDRAM, and NOR Flash in a 19x19x3.9mm package

by Xilinx Employee ‎09-08-2014 03:26 PM - edited ‎09-09-2014 06:50 AM (837 Views)

The 3D Plus Fusio-II module uses 3D stacking to place four die—a Xilinx Spartan-6 XQ6SLX150T FPGA, two mobile DDR (mDDR, also known as LPDDR) SDRAMs, and NOR Flash device—along with 167 bypass capacitors filtering 10 power supplies in a 19x19x3.9mm package. The module has a smaller pcb footprint than the Spartan-6 FPGA it incorporates—361mm2 versus 937mm2. Here’s a photo of the packaged device:

 

 

3D Plus Fusio-II Module.jpg

 

 

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Xilinx design tools include the configurable MicroBlaze soft processor core with a configuration tool. Configurable processors make interesting benchmarking targets. The ability to tailor a processor architecture to a target application allows you to trade off performance against on-chip resources. Tailoring can drastically increase a program’s execution speed and it can drastically increase or decrease the amount of on-chip resources needed to implement the processor. The following table shows the relative performance of three different Xilinx MicroBlaze processor configurations (minimal, intermediate, and maximum performance) over four EEMBC benchmark suites.

 

 

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Swipe these Low Cost FPGA-based MIPI DSI and CSI-2 Interfaces for Video Displays and Cameras

by Xilinx Employee ‎09-08-2014 11:07 AM - edited ‎09-08-2014 02:17 PM (897 Views)

MIPI’s DSI (Display Serial Interface) and CSI-2 (Camera Serial Interface 2) have become industry-standard, low-cost interfaces to video displays and cameras across a wide variety of embedded systems and you can now connect Xilinx FPGAs to these low-cost devices and other MIPI-compatible ASSPs using these interfaces in high-bandwidth applications supporting 4K2K and beyond. Even better, the free Xilinx App Note XAPP894 shows you how to do this in great detail. This App Note published late last month is a follow-up to the IEEE Webinar and working demo discussed last March in a previous Xcell Daily blog. (See “How to Drive Multiple Live Cameras and Displays for Pennies—A Free IEEE Spectrum webinar.”)

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Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

by Xilinx Employee ‎09-08-2014 10:01 AM - edited ‎09-08-2014 01:51 PM (995 Views)

 

By Adam Taylor

 

In the last blog, we had the Zynq SoC up and running using both ARM Cortex-A9 MPCore processor cores using AMP—asymmetric multiprocessing. However I did not talk much about the software running on the processors because the blog was already rather long.

 

The software I have up and running on both cores is very simple. Its simplicity allows me to show you how to get the two Zynq SoC processor cores communicating via the OCM (on-chip memory). However, the software is doing simple things at the moment so that we have a baseline to move on from.

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About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, embedded systems design, design IP, EDA, and programmable logic.