Need a development platform for a high-speed PCIe card? Look no further than HiTech Global’s HTG-K800, a PCIe Gen3 x8 card with one of three Xilinx Kintex UltraScale FPGAs on board: the KU060, KU085, or KU115.




HiTech Global HTG-K800 PCIe Platform.jpg



HiTech Global HTG-K800 PCIe Gen3 x8 Card



Here’s a block diagram of the card:




HiTech Global HTG-K800 PCIe Platform Block Diagram.jpg



In addition to the Kintex UltraScale FPGA, other key features of the card include:


  • 2.5Gbytes of 72-bit DDR4-2400 SDRAM
  • Two HPC (High Pin Count) FPGA Mezzanine Connectors, each with 160 single-ended I/O pins (total of 320) and 10 GTH Serial Transceivers (total of 20)
  • High-Speed PCIe Gen3 x8 bus


I received an email this morning from “the Embedded Centric” telling me about a terrific new free training course for the Zynq-7000 SoC based on the Avnet ZedBoard. It’s really a full-featured embedded design course featuring the Zynq SoC, which is one really powerful embedded controller—able to tackle just about any embedded application you can throw at it.



Avnet ZedBoard.jpg



Avnet ZedBoard based on the Xilinx Zynq-7000 SoC



The training presently consists of eleven individual labs including:



The Embedded Centric site is the brainchild of Ali Aljaani, an embedded systems engineer with a Master’s degree in Computer Architecture and a minor in Software Engineering, who is currently working as a teaching assistant at Texas A&M University at Qatar. Aljaani teaches classes on Microprocessor Systems Design, Computer Architecture and Design, Digital Systems Design, Computer Programming and Algorithms.



The Three Ages of the FPGA: Your PDF hymnal is now ready

by Xilinx Employee ‎08-26-2015 02:32 PM - edited ‎08-26-2015 04:10 PM (395 Views)

Last month, Xcell Daily posted a 40-minute presentation by Xilinx Fellow Dr. Steve Trimberger on “The Three Ages of the FPGA” that he gave at the University of Toronto. (See “Video: The Three Ages of the FPGA and the Age of the Design Engineer.”) If you watched that video and wished you had a hard copy of Trimberger’s presentation so you could follow along at home, you’ll find a PDF version of the presentation attached to this blog post, below.


If you weren’t one of the 2400 people who watched the video, now you can download the presentation and follow along. Trimberger’s talk walks you through the three ages of the FPGA:


  1. The Age of Invention: When the architecture of the month dominated and FPGAs were smaller than the overall system design problem.
  2. The Age of Expansion: When FPGAs started to chase after ASICs and FPGA capacity started to approach the size of the overall system-design problem, driven by IC process technology.
  3. The Age of Accumulation: When FPGA design started to embed large functional blocks including microprocessors; memories; DSPs; and leading-edge, high-speed SerDes ports.


3-part Video Series Teaches You How to Use Micrium’s µC/OS-III RTOS with the Xilinx Zynq SoC

by Xilinx Employee ‎08-26-2015 11:33 AM - edited ‎08-26-2015 11:44 AM (405 Views)

Micrium has just published a 3-part video series on using its µC/OS-III RTOS with the Xilinx Zynq SoC. Here are all three videos collected together for your convenience.




Pair of Spartan-6 FPGA boards bring extensive analog and digital I/O to XMC form factor

by Xilinx Employee ‎08-26-2015 11:05 AM - edited ‎08-26-2015 11:05 AM (295 Views)

TEWS Technologies has introduced two XMC board families based on Xilinx Spartan-6 FPGAs that provide the system builder with myriad analog and digital I/O options. The TEWS TXMC633 cards are standard single-width XMC modules that provide 64 ESD-protected TTL I/O lines with a pull-up/pull-down resistor connected to 3.3V, 5V, or ground. There are four versions:


  • –x1R: 32 EIA-422/EIA-485-compatible, differential I/O lines
  • –x2R: 32 single-ended TTL and 16 differential I/Os
  • –x3R: 32 differential, multipoint LVDS transceivers
  • –x4R: 32 single-ended TTL and 16 differential, multipoint LVDS transceivers


Here’s a photo of the TEWS TXMC633 card:



TEWS Technologies TXMC633-23R XMC Module.jpg




Here’s a block diagram of the TEWS TXMC633 card:



TEWS Technologies TXMC633-23R XMC Module Block Diagram.jpg 



The TEWS TXMC635 cards are standard single-width XMC modules that provides 48 ESD-protected TTL I/O lines with a pull-up/pull-down resistor connected to 3.3V, 5V, or ground; eight 16-bit analog output channels; and 32 analog inputs configurable as 32 single-ended or 16 differential 16-bit channels samples at a maximum rate of 1Msamples/sec.


Here’s a photo of the TEWS TXMC635 card, sans heat sink:



TEWS Technologies TXMC635-10R XMC Module.jpg



Here’s a block diagram of the TEWS TXMC635 card:



TEWS Technologies TXMC635-10R XMC Module Block Diagram.jpg



Both XMC Module families can be loaded with a Xilinx Spartan-6 LX45T or LX100T FPGA, which connect to the host system via a PCIe port. Configuration can be done through the PCIe port or via the on-board, in-system programmable SPI Flash memory. The Spartan-6 FPGAs are connected to 128Mbytes of DDR3 SDRAM, controlled by the SDRAM controller in the FPGAs.





Arduinos are extremely popular, low-cost, 8-bit microcontroller boards with somewhat limited processing power but with a long list of compatible shields capable of all sorts of common, unusual, and just plain weird interfacing. Want to boost that processing power by three orders of magnitude or so? Make a Zynq-based shield based on the Arduino board footprint. That’s exactly what a new project on Hackaday creates: an open-source Arduino-compatible Zynq shield. The Zynq shield essentially replaces the Arduino’s 8-bit processor with a dual-core, 32-bit ARM Cortex-A9 MPCore processor and the Arduino’s few kilobytes of SRAM with 64Mbytes of LPDDR2 SDRAM.




Zynq Arduino shield.jpg





Avnet handles Xilinx All Programmable devices and power products from IR, now an Infineon Technologies company. So it makes perfect sense that Avnet would be demonstrating an UltraScale eval board, specifically a Kintex UltraScale board, running on power supplied by IR/Infineon's PMBus SupIRBucks integrated POL (point of load) converters.


This is an engineering feel-good story if there ever was one. Disabled people who have trouble walking and climbing stairs face enormous obstacles in everyday life. A large student engineering and design team at ETH Zurich (the Swiss Federal Institute of Technology) tackled the challenge of mobility for disabled people and the result is, honestly, breathtaking. The team developed a powered wheelchair dubbed Scalevo that balances on two wheels like a Segway. When faced with stairs, the wheelchair shifts into tracked mode by lowering a pair of rubber tank tracks that handle steps with aplomb.



Scalevo Wheelchair.jpg




Tata Motors Bus.jpgTATA Motors is India’s largest automobile company and the world’s fourth largest bus manufacturer. For one of the company’s upcoming parallel hybrid buses, TATA’s Advanced Integration Team needed to integrate all the ECUs and other electronic components in a lab environment for extensive testing and to validate the vehicle’s electronic system integration using a hardware-in-the-loop (HIL) test. The results of the integration test would significantly help with the vehicle’s ECU software development and with the evaluation of options offered by multiple vendors.


Here’s where this engineering story gets really interesting because this team did what few other teams do: it took two very different development paths and is therefore able to directly compare the two results.



London’s large population has been subjected to air-quality problems for more than 100 years. First it was coal smoke and later, petrochemical smog. How do you fight that? Develop more efficient ways to extract and use energy. Vantage Power is doing just that by developing a retrofit power plant for London’s double-decker buses. The company’s B320 B320 Diesel/electric hybrid power system is a bolt-in, form-fit-and-function replacement for the buses’ existing Diesel power plant that reduces emissions and fuel consumption by 40%–an annual savings of about £20,000 per bus—with a zero-emission mode that will take the bus 4km. There are approximately 8700 buses operating in London and 47,000 buses operating around the UK. Some of the UK’s larger bus fleets have as many as 7500 vehicles. These buses are not cheap. Replacement hybrid buses cost upwards of £350k. Refurbishing existing buses makes a lot of economic and environmental sense. Currently, Vantage Power is focusing on developing the B320 System for the UK’s four most popular double-decker bus models: the Alexander Dennis Trident II and E400 and Volvo’s B7TL and B9TL.



Vantage Power Hybrid Bus Conversion.jpg



The Vantage Power B320 System relies on a small Diesel engine connected to a generator that charges the system’s batteries. The batteries then power the electric motor that drives the vehicle’s gearbox and wheels. The control system for this hybrid power plant is necessarily complex. Information from the pedal control (throttle) flows over a CAN bus to the B320 System controller, which manages the power train by delivering power to the electric motor, monitoring and managing the charge in the batteries and the battery operating temperature, and operating the Diesel engine when needed based on the vehicle’s speed, the desired speed, and the state of charge in the batteries.


The B320 System’s controller interfaces with more than 32 different input and output ports and devices and controls more than 13 other devices including the electric motor, the Diesel engine, fans, and pumps. In all, the controller must handle 4981 network variables in real time. It’s all done by a National Instruments’ (NI) CompactRio controller programmed entirely in the company’s LabVIEW and LabVIEW Control Design and Simulation Module. The system programming relies on the real-time capabilities of the CompactRIO controller, supplied by a Xilinx Kintex-7 FPGA.


Free downloadable PDF workbook for Digilent Zybo and Avnet ZedBoard Zynq SoC Eval Boards. Get it now!

by Xilinx Employee ‎08-24-2015 01:51 PM - edited ‎08-28-2015 05:12 AM (1,169 Views)

Last year, Louise Crockett, Ross Elliot, Martin Enderwitz, and Robert Stewart at the University of Strathclyde’s Department of Electronic and Electrical Engineering published “The Zynq Book,” which you can download as a free PDF. You can also purchase a hard copy of The Zynq Book on Amazon for $27. Just in case you’ve not been paying attention, the Zynq SoC fuses the easy software programmability of a dual-core ARM Cortex-A9 MPCore processor with the outstanding hardware performance of Xilinx programmable logic.


But wait, now there’s more.


Crockett and Stewart have now published a comprehensive, step-by-step companion tutorial workbook targeting the low-cost, Zynq-based Digilent Zybo and Avnet ZedBoard. It’s dated August, 2015, so you know it’s hot off the press. As with The Zynq Book (more than 20,000 people downloaded the book PDF), the workbook is now available as a free PDF download (click here). (In addition to the free PDF, you can order a $14.95 hard copy of the new 178-page workbook from Amazon or Barnes and Noble.)




Tutorial Workbook for The Zynq Book.jpg




This book holds your hand while you enter the world of Zynq SoC configuration and programming using the Xilinx Vivado Design Suite, from starting a project to writing software with SDK (the Software Development Kit), to using existing hardware IP and creating your own. This is a killer companion to The Zynq Book.


Go download your copy now.


Adam Taylor’s MicroZed Chronicles Part 97: SDSoC In depth Example Part 4

by Xilinx Employee ‎08-24-2015 11:13 AM - edited ‎08-24-2015 11:14 AM (1,413 Views)


By Adam Taylor


In the last blog we finished the AES algorithm explanation and understood the steps needed for encryption, decryption, and key expansion. This blog looks at the C code needed to implement the AES algorithm in software, so that we can initially baseline the software code prior to offloading it to the PL (programmable logic) side of the Zynq SoC. Because key expansion is only performed once, when the key is changed, I am not going to accelerate the key expansion. I am only planning to accelerate the forward encryption path.


To ensure that the algorithm is implemented correctly, I will be using the NIST AES FIPS standard examples and then comparing against my results using the Zynq SoC.


If you want a snapshot view of climate change, the thickness of polar sea ice is a good place to look. Sea ice is always covered by snow that’s several meters thick and this snow modulates the heat exchange rate between ice and atmosphere. So measuring the thickness of the snow over the sea ice helps to understand changes in the ice thickness. The Center for Remote Sensing of Ice Sheets (CReSIS), established by the National Science Foundation (NSF) in 2005, develops new technologies and computer models to measure and predict how sea level will change based on the mass balance of ice sheets in Greenland, Antarctica, and the Arctic Ocean. CReSIS is using specially developed, mission-specific, snow-penetrating radar to help it develop these models. CReSIS developed its flyable snow radar using National Instruments’ LabVIEW graphical System Design Software and the company’s PXIe FlexRIO hardware.


Radar signal reflection occurs at both the air-snow and snow-ice interfaces and you can use the relative timing of these radar reflections to determine snow thickness. Most radars use pulsed transmission but CReSIS’ snow-penetrating radar uses frequency-modulated continuous wave (FMCW) RF to reduce the transmission power and to achieve higher compression gain. This system can resolve snow layer thicknesses to a few centimeters.


The radar transmitter employs DDS (direct digital synthesis) using a 2.5GHz clock to generate the baseband signal, which is passed to a frequency multiplier that generates an RF signal, which is then fed to an RF power amplifier and the transmitting antenna. The radar’s receiver amplifies and filters the received reflection signal from an 8x1 MIMO antenna array, digitizes each of the received signals from the eight antennas, uses digital beamforming to improve the SNR and clutter rejection and DDC (digital down conversion) and to reduce data rates. The receiver section then de-ramps the resulting waveform with the transmitted reference signal to remove interference from the FMCW transmitter. Signal processing including DDC, decimation, and beamforming is performed by a National Instruments PXIe-7975R FPGA Module for PXI Express, which incorporates a Xilinx Kintex-7 K410T FPGA. Data is stored in a RAID drive array. The CReSIS development team used NI’s LabVIEW graphical development software to develop complicated tasks such as the radar system’s graphical user interface and the many radar-receiver signal processing functions performed by the Kintex-7 FPGA.


The entire system fits in a small rack, as shown below:



Snow Radar Rack System.jpg


CReSIS Snow Radar Rack System based on an NI PXIe Chassis




A team from the Naval Research Laboratory and CReSIS conducted airborne radar surveys over the Arctic Ocean using this snow radar system installed in a DHC-6 Twin Otter aircraft. The figure below shows an echogram output from the system:




Snow Radar Echogram 2.jpg



CReSIS Snow Radar Echogram




To date, the CReSIS snow radar has flown on more than 48 sea ice flights. During these flights, the snow radar’s digital receiver successfully recorded direct snow thickness measurements over large areas of Arctic and Antarctic sea ice for the first time.


This work was a finalist in the RF and Communications category at the NI Engineering Impact Awards ceremony held earlier this month in Austin, Texas in conjunction with NI Week. You can read NI’s full case study of this project by clicking here.

I love it when cool new Zynq-based designs just drop out of the sky. Here’s a very short video just posted on YouTube from ELMG Digital Power in New Zealand demonstrating a graphical vehicle dashboard. The ELMG demo runs on a Zynq-based Avnet MicroZed plugged into an I/O carrier card:






The really interesting part of this demo is the international array of Zynq-compatible software components ELMG used to create this demo:


  • The automotive dash cluster is built with QT Graphics headquartered in Helsinki.
  • The graphics control IP is programmed from Xylon’s LogicBricks LCD controller and 2D GPU. Xylon is in Croatia.
  • The dash widgets are based on code from in Poland.
  • The system runs ubuntu linux from, well, cyberspace.




The World Bank estimates that some 400 million people in India lack consistent (or any) access to electrical power because of geographic isolation and fuel shortages. Much of rural India is fairly remote from power stations. This situation has a huge negative impact on the standard of living in these areas because children often enter their villages’ fresh water supply chain, carrying water from the source to their homes, rather than go to school. There’s also a lack of communication with the outside world. Local power generation through decentralized, distributed solar photovoltaic (PV) systems installed on individual houses promises to rectify this situation but when an individual house system breaks down, that house has no power. There’s no redundancy in a system based on many unconnected individual solar systems.


FluxGen Engineering Technologies Pvt. Ltd. In Bangalore has developed a system called the Smart Renewable Energy Micro-Grid that optimally aggregates the power from various power sources including PV arrays, wind generators, batteries, and electrical generators powered by fossil fuels like Diesel. For distributed PV arrays, the system can connect individual panels in series and parallel arrangements to maximize the overall output power.




FluxGen Micro-Grid Lab setup.jpg


FluxGen Micro-Grid Lab Setup



The goal is to make renewable energy cost competitive and reliable, according to FluxGen’s Managing Director Ganesh Shankar.


The Open Source Virtual Reality (OSVR) Consortium wants to create an open-source environment for all sorts of software and equipment vendors with the aim of greatly expanding the applications and number of users involved in the world of VR. OSVR was co-founded by Razer, a world leader in high-performance gaming hardware, software, and systems.



OSVR Goggles Exploded Diagram.jpg 


Xilinx has been listed as an OSVR supporter on the Consortium’s Web site for a while. The relationship just got a little more formal because today’s Xilinx press release announced that the company’s All Programmable devices were enabling the OSVR Hacker Development Kit.


Last month, the consortium started shipping a relatively low-cost Hacker Development Kit and related components to interested developers. Open source schematics and a BOM for the kit components have been available since at least March. If you take a look, you’ll find a Xilinx Spartan-6 FPGA on the kit’s HDMI board. That’s not a surprise. Xilinx All Programmable devices provide any-to-any connectivity and programmable hardware-level computational performance. Both attributes are essential when trying to connect diverse VR devices and handle multiple data formats from many vendors.




If you need to lock a gigabit transceiver’s output to an input source, you might already be familiar with using VXCOs (voltage-controller crystal oscillators) to accomplish this feat. Problem is, if you have a lot of transceivers to tame, the cost in external VXCOs adds up. A new application note, XAPP1241, titled “All Digital VCXO Replacement for Gigabit Transceiver Applications (UltraScale FPGAs)” shows you how to fight transceiver jitter using digital PLLs (DPLLs) built using the high-speed transceivers and programmable logic fabric in Xilinx UltraScale devices. (Note: Some of the high-speed transceivers in Xilinx UltraScale devices can operate at 30.5Gbps.) The reference design circuit provided with the app note can lock an individual transceiver greater than ±1000ppm from the reference oscillator and programmatically provide jitter cleaning bandwidths in the range from 0.1 Hz to 1 KHz. The system applications and operational theory in this new app note are equivalent to the 7 series application note, “All Digital VCXO Replacement for Gigabit Transceiver Applications (7 Series/Zynq-7000),” XAPP589.


Grid-scale, 420kW Energy Pod built from fourteen 30kW, Zynq-controlled Zinc-flow batteries

by Xilinx Employee ‎08-18-2015 11:56 AM - edited ‎08-18-2015 12:05 PM (1,111 Views)

Chances are pretty good that you’ve never heard of a zinc-flow battery, which is an electrochemical cell that reversibly converts chemical energy directly to electricity and vice versa. A flow battery resembles a more conventional electrochemical cell but the electrolyte is not stored in the cell around the electrodes. Instead, the liquid electrolyte is stored in tanks outside of the cell and then pumped into the cell as needed to generate electricity. You don’t make little portable AA cells or laptop batteries from this kind of battery technology. In fact, Primus Power makes 30kW (72kWh) batteries from zinc-bromine cells. They’re a lot larger than AA cells or laptop batteries. Here’s a photo:



Primus Power Zinc-Flow Battery.jpg



Primus Power 30kW Zinc-Flow Battery



Primus uses one Zynq-based National Instruments’ CompactRIO cRIO-9068 programmed with the company’s LabVIEW graphical development environment and LabVIEW FPGA Module to control each zinc-flow battery. The NI cRIO-9068 manages the zinc-flow battery’s electrochemical charging and discharging processes by directly controlling and monitoring a variety of pumps, valves, and sensors.


What could possibly be more appropriate than using a Zynq SoC to manage a zinc-flow battery?


Wi-Fi RF energy permeates most indoor spaces these days and some researchers at University College London theorized that this ambient energy field could be used to see through walls.


Turns out, they were correct.


The researchers have proved their thesis by successfully developing a demonstration system capable of passively tracking moving human bodies through thick, brick walls using National Instruments’ (NI) LabVIEW and two of the company’s USRP-2921 SDR platforms. The demo system emits no additional RF energy for detection; it merely uses the ambient Wi-Fi RF already injected into the air from existing Wi-Fi access points. Therefore, the use of this equipment is essentially undetectable, which has extremely interesting implications for military and security surveillance applications, as illustrated by this image:



Passive Wi-Fi Radar System.jpg



This passive Wi-Fi radar scheme requires two receivers to perform ambiguity analysis. The first receiver implements a reference channel that’s locked onto the base radio signal (from a Wi-Fi router). The other receiver implements the surveillance channel by measuring the RF reflections from moving targets.



Here’s a diagram of the demo system setup:



Passive Wi-Fi Radar System Setup.jpg



Simplistically, this system determines the velocity and position of a target by comparing the reference and surveillance signals. However, reality is not so simple. The system must perform advanced ambiguity analysis, cross correlation, Fourier transformation, and intelligent error detection to generate a usable output. The researchers employed NI’s LabVIEW graphical development environment to program this system.


Two detection scenarios demonstrated the system’s capabilities. In the first scenario, a person simply walked behind a 25cm-thick brick wall. The goal in this scenario was just to detect the person. In the second scenario, the goal was to detect body gestures made by the same person behind the same brick wall. At this point in the development, the system not only detects the person behind the wall, it also can detect small hand gestures.


This work won an award in the RF and Communications category at the NI Engineering Impact Awards ceremony hel earlier this month in Austin, Texas in conjunction with NI Week. You can read NI’s full case study of this project by clicking here.


Note: A Xilinx Spartan-6 FPGA inside each NI USRP-2921 SDR platform provides the required hardware configurability and real-time performance.




Fujitsu has a growing wireless infrastructure business including CPRI-compliant BBUs (baseband units) and RRHs (remote radio heads). The company has also focused on developing BBUs and RRHs based on ORI (ETSI’s Open Radio equipment Interface), which in turn is based on CPRI but includes upper-layer protocol standardization. (ETSI is the European Telecommunications Standards Institute). To prove out independently developed ORI-based BBUs and RRHs, Fujitsu needed an ORI-compliant test system that could independently test those units. Fujitsu chose an existing CPRI-compliant RRH tester from National Instruments (NI) and, using the tester’s built-in programmability, modified the tester’s CPRI component so that it became ORI compliant.


NI’s RRH tester consists of a PXI-based chassis, controller, high-speed serial module, RF attenuator, and a Vector Signal Transceiver (VST), as shown below:



NI RRH Tester.jpg


NI’s RRH tester



The flexible and highly programmable NI VST is the RF heart of this tester. (See “National Instruments’ 6GHz Vector Signal Transceiver gets bandwidth, FPGA upgrades.”). Part of the VST’s programmability is based on Xilinx Virtex-6 FPGAs. In addition, the tester includes an NI PXIe-6592 High-Speed Serial Module for PXI Express, based on a Xilinx Kintex-7 FPGA, to implement the CPRI protocol. It’s the FPGA programming in this card that Fujitsu and NI modified to produce a version that implemented the ORI-compliant protocols.



Net result: ORI-compliant BBUs and RRHs from different vendors were tested and confirmed to be interoperable with just a half-day’s testing. In addition, the modified tester permitted Fujitsu to verify that there were “no omissions or oversights in the ORI specification.”



This project was a finalist in the Consumer Electronics Test category at the NI Engineering Impact Awards, held earlier this month in Austin, Texas in conjunction with NI Week. You can read NI’s full case study of this project by clicking here.


The European wireless eCall system is designed to issue emergency calls throughout the EU when a vehicle is involved in a significant accident. The in-vehicle eCall device automatically dials 112 in the event of a serious road accident, and wirelessly sends airbag deployment, impact sensor information, and GPS coordinates to local emergency agencies. According to some estimates, eCall could speed emergency response times by 40 percent in urban areas and by 50 percent in rural areas.


As more eCall devices are installed in new vehicles, reducing production test time becomes increasingly important. Using National Instruments’ (NI) TestStand, LabVIEW, and Wireless Test System (WTS), Harman—an international audio and vehicle infotainment product manufacturer—teamed with NOFFZ--a system integrator for PC-based measurement and automation solutions—developed a flexible, fully programmable tester capable of performing high-speed, end-of-line tests on all sorts of wireless products including eCall devices as well as other products based on WLAN, Bluetooth, cellular, and global navigation system wireless frequencies and protocols. The result is a multi-DUT (device under test) tester called the NOFFZ UTP 9010 that executes final tests in “significantly shorter” times than the test equipment being replaced.



NOFFZ UTP9010 Wireless Test System.jpg



Adam Taylor has just self-published a hardcopy edition of his first year of MicroZed Chronicles blogs featuring the Xilinx Zynq SoC. If you are looking for a way to ease into the Zynq waters bit by bit, Adam’s chronicles are a really great choice.



MicroZed Chronicles hardcopy.jpg



The book is available on the Web site. Click here to go straight to the order page.


Of course, you can still order the Amazon Kindle edition of the MicroZed Chronicles as well.




By Adam Taylor


Having explained the detailed steps needed for the AES encryption and decryption algorithms, we now need to know the order in which these steps are applied within a round and whether we apply all of these steps for each round or just some of them.


Each AES encryption round consists of the following ordered steps:


  1. Substitute Bytes
  2. Shift Rows
  3. Mix Columns (for rounds 1 to N-1 Only)
  4. Add Round Key – using the expanded key


Important note: the final round does not contain the Mix Columns stage.


Of course we need to be able to reverse the process and turn the unreadable ciphertext back into plain text so that the encrypted information will be useful.


The inherently modular nature of National Instruments’ (NI) test instruments plus LabVIEW programmability permits the company to quickly assemble more complex instrumentation products from the company’s existing products. Such was the case with last year’s introduction of the PXI-based NI Semiconductor Test System. New year; new market. Last week, NI introduced the Wireless Test System for production testing of wireless devices, based on a pair of NI Vector Signal Transceivers (VST) plugged into a PXI chassis and fronted by a multiport RF switch.



NI Wireless Test System.jpg



NI Wireless Test System is based on two of the company’s PXI Vector Signal Transceivers



NI’s WTS has the flexibility to test all sorts of wireless products using RF bands and protocols including LTE Advanced Cellular, Bluetooth, Wi-Fi, and GPS. The inherent programmability of the instrument permits NI and NI’s customers to adapt the WTS to any sort of RF product.


Part of the WTS’ programmability is based on the FPGAs inside of the NI VSTs—which are Xilinx Virtex-6 devices (see “National Instruments’ 6GHz Vector Signal Transceiver gets bandwidth, FPGA upgrades.”). The programmable I/O and computational capabilities of the Virtex-6 FPGAs in the VSTs are accessible through NI’s LabVIEW FPGA Module, which greatly expands the types of real-time testing that’s possible with the VSTs and the WTS.


NVMe over Fabric: A cloud application just made to be solved with an FPGA implementation

by Xilinx Employee ‎08-14-2015 01:36 PM - edited ‎08-14-2015 02:12 PM (1,794 Views)

Space is big. Really big. You just won't believe how vastly, hugely, mind-bogglingly big it is. I mean, you may think it's a long way down the road to the chemist, but that's just peanuts to space.” – Douglas Adams, “The Hitchhiker's Guide to the Galaxy”


Douglas Adams might as well have been writing about data storage in data centers and the cloud. While NVMe is a great storage interface protocol for PCIe systems (which are spatially compact), something more is required for a widely distributed storage network that uses Ethernet or other networking communications. Something you might find in a data center or in a cloud of data centers. Something that looks like this:



NVMe over Fabric Block Diagram.jpg



Enter NVMe over Fabric, or NVMeOFabric, a concept that extends NVMe’s benefits far beyond the reach and scalability of PCIe.


FPGAs with their any-to-any programmable I/O and programmable logic capabilities are great for implementing NVMeOFabric systems. Xilinx UltraScale All Programmable devices are especially well suited to such designs with their PCIe Gen3 hard cores; high-speed SerDes ports; and pre-verified IP for 10/40/100G Ethernet ports, NVMe, and SSD controllers (including the just-introduced LDPC error-coding IP, see “Fast LDPC IP core for Flash-based cloud and data-center storage applications is optimized for FPGA implementation”). In fact, this was the precisely topic of a presentation titled “FPGA-Based Design for Large-Capacity Fabric-Based NVMe Storage Systems,” given by Shreyas Shah, Principal Data Center Architect at Xilinx, and an in-booth demo at this week’s Flash Memory Summit held in Silicon Valley. So all of this NVMeOFabric stuff is not merely theoretical, it’s operational—at least at the demo level.



Earlier this week, Xilinx introduced a new LDPC (low-density, parity-check) LogiCORE IP block specifically for the unique requirements of Flash-based cloud and data-center storage applications. This LDPC IP core achieves 400MHz performance in both the Xilinx UltraScale and 7 series All Programmable devices and requires half the resources of alternative IP offerings—which directly translates into lower power operation. As memory-cell feature sizes shrink on Flash devices, endurance falls and uncorrectable bit-error rates rise. Consequently, Flash-memory controllers in SSDs must employ more sophisticated error-correction codes and algorithms to bring the system-level error rate back up to acceptable levels. It’s precisely for this reason that in-vogue BCH error codes are running out of steam and LDPC codes—with near-Shannon-limit capability—are coming into use. This graph of corrected bit-error rate versus raw bit-error rate from a Xilinx presentation at this week’s Flash Memory Summit tells the entire story:



LDPC Error Correction vs BCH.jpg



As the graph shows, LDPC hard-decision error-detection and correction offers some improvement over BCH codes but LDPC soft-decision error-detection and correction offers significant improvement. The new Xilinx LDPC LogiCORE IP block supports both hard- and soft-decision decoding.


The new Xilinx LDPC IP core has been successfully tested on a Xilinx KCU105 Eval Kit with a custom-built NAND Flash card plugged into the Kit’s FMC connector. Here’s a photo:



Xilinx KCU105 with NAND Flash for LDPC Demo.jpg




“We evaluated several systems on modules (SOMs) and embedded single-board computers (SBCs), and there is no comparison to the software integration offered by NI. We estimate that our time to deliver with the NI SOM is a tenth of the time using alternative approaches because of the productivity gains of NI’s approach to system design, particularly with NI Linux Real-Time and the LabVIEW FPGA Module.”—Sébastien Boria, Airbus


Last year at NI Week 2014, Airbus took to the keynote stage to showcase its vision for making aircraft-building tools based on augmented reality. (See “Augmented reality to drive Airbus’ Factory of the Future—powered by Xilinx Zynq SoC.”) This year, Airbus has moved from vision to implementation. Airbus is launching the development of three smart tool families that perform different manufacturing processes: drilling, measuring, and quality data logging and tightening. The National Instruments (NI) Zynq-based sbRIO-9651 SOM serves as the foundation for all of these tools, which are developed using NI’s LabVIEW and prototyped on NI’s Zynq-based CompactRIO NI-9068 controllers. Software compatibility between the sbRIO SOM and the CompactRIO controller allow the Airbus development teams to validate their design concepts quickly by integrating IP from existing Airbus libraries and open-source algorithms.



Airbus Smart Tools.jpg



The Airbus smart-tool development team evaluated several SOMs and embedded single-board computers (SBCs) and found that “there is no comparison to the platform-based design approach and the hardware-software integration offered by NI.” They estimate that the “time to deliver with the NI SOM is a tenth of the time using alternative approaches because of the productivity gains of NI’s approach to system design, particularly with NI Linux Real-Time and the LabVIEW FPGA Module.” NI’s LabView and LabVIEW FPGA along with the tight hardware integration with the NI SOM and CompactRIO controller allows the team to “focus more on the key features of our system such as image processing on FPGAs.” In other words, the NI offerings allow the Airbus smart-tools development engineers to focus on the parts of the project that differentiate their designs by handling the common development tasks shared by all embedded projects.


This work was a finalist in the Aerospace and Defense category at the NI Engineering Impact Awards ceremony held last week in Austin, Texas in conjunction with NI Week. You can read NI’s full case study of this project by clicking here.







Two days ago, UrtheCast (Earth Cast) posted this first-light video from its Theia medium-resolution video camera, which is bolted to the International Space Station (ISS):





UrtheCast’s Theia camera has a 5m/pixel resolution from its perch 400km above the Earth’s surface. The company’s newest camera, the Iris HRC (High-Resolution Camera) with 1m/pixel resolution, just achieved initial operating capability yesterday. You don’t get such imagery, much less video with 5x the linear resolution, by suction-cupping a commercial mobile phone to the ISS’ outer hull. You need to develop a very special camera.


Cancer-fighting drugs are highly toxic; that’s why they kill tumor and cancer cells. So you want to use as little of the drug as possible while still delivering enough to kill all of the cancer—which means you want to deliver the drug to exactly the right place with as little delivered elsewhere as possible. You could slice the patient open and pour the drug on the tumor directly. As it turns out, there might be a better, less invasive way to deliver drugs to the right location without the need for incisions using focused ultrasound and bubble cavitation. That’s the focus of research currently underway at the University of Dundee’s Institute of Medical Science and Technology (IMSat) in the UK.


Ultrasound is already a staple of medical treatment but bubble cavitation is generally avoided because it can damage tissue if not closely controlled. IMSaT’s Cavitation Research Group working in conjunction with Diagnostic Sonar Ltd. (DSL) wants to create a new therapy that uses focused cavitation to disrupt cancer tissues, making them far more susceptible to cancer-killing drugs. Essentially, they want to “fizz” cancer tumors out of existence.


DSL has three decades of experience with ultrasound-based applications. The company’s FI Toolbox includes hardware and software modules for high-performance ultrasonic data acquisition and imaging. DSL currently relies on the National Instruments’ (NI) LabVIEW, LabVIEW FPGA, and FlexRIO platform for real-time ultrasound control and the cancer-fighting research at IMSat certainly requires real-time ultrasound control. Experiments required a control feedback loop to control ultrasound intensity that would operate deterministically at 10KHz—that’s a 100μsec cycle time—using FFT calculations to modulate the intensity of the ultrasound based on real-time observations from a high-speed camera capturing images as fast as 500,000 frames/sec.


That’s no job for a microprocessor. It takes an FPGA.


Here’s a diagram of the IMSaT/DSL ultrasound experimental setup:



IMSaT DSL Ultrasound Experimental Setup.jpg




The NI-7966 FlexRIO FPGA Module shown in the above image is based on a Xilinx Virtex-5 SX95T. You will find Xilinx Virtex-5, Spartan-6, and Kintex-7 FPGAs and Zynq SoCs in all of NI’s FlexRIO, CompactRIO, Single-Board RIO, myRIO, and roboRIO products as well as the just-announced Controller for FlexRIO (see “NI’s new, embeddable FlexRIO Controller compresses PXI chassis down to one slot dedicated to I/O”).


By using NI’s LabVIEW throughout the project, the development team could write application code that ran initial simulations on a PC using previously acquired data. Once the code proved viable, the team simply moved its LabVIEW application over to NI’s FlexRIO hardware using LabVIEW FPGA to produce a real-time system without the need to learn another programming language or to take time for code porting. Coding transparency in the same LabVIEW environment across PC, real-time, and FPGA platforms was critical to getting a working proof of concept in just six months.


Here’s a photo of the real-time control hardware, based on NI’s PXI platform and additional, ultrasound-specific hardware developed by DSL:



DSL 16B Modular Ultrasonic Array Acquisition and Imaging Box.jpg



This project successfully demonstrated that ultrasound-generated bubble cavitation can be controlled using high-speed refresh rates. This finding is not only useful for medical therapies but for industrial applications including sonochemistry and precision acoustic cleaning as well.


This work was a finalist in the Advanced Research category at the NI Engineering Impact Awards ceremony held last week in Austin, Texas in conjunction with NI Week. You can read NI’s full case study of this project by clicking here.






NI’s new, embeddable FlexRIO Controller compresses PXI chassis down to one slot dedicated to I/O

by Xilinx Employee ‎08-12-2015 02:48 PM - edited ‎08-12-2015 02:55 PM (1,535 Views)

National Instruments’ (NI) LabVIEW-programmable FlexRIO instruments for PXI and PXI Express consist of two components: NI’s FlexRIO FPGA Modules based on Xilinx Kintex-7 and Virtex-5 FPGAs and FlexRIO Adapter Modules that provide high-performance analog and digital I/O. The FlexRIO FPGA modules plug into the PXI chassis and the interchangeable adapter I/O modules protrude out of the front of the chassis. This FlexRIO system architecture creates a powerful, flexible way to build instruments, but what if you want to build a relatively small embedded system and you only need one FlexRIO Adapter Module? NI apparently heard that question often enough because the company has just introduced a 3-member family of small, rugged Controllers for FlexRIO that accept one FlexRIO Adapter Module each. All three controllers incorporate NI’s own sbRIO-9651 SOM, an industrial-grade processor module based on the Xilinx Zynq Z-7020 SoC. (See “NI’s new Zynq-in-a-box SOM targets embedded development with dual-core ARM Cortex-A9.”


The three new NI Controllers for FlexRIO are:


  • The NI 7931R with a Xilinx Kintex-7 325T FPGA
  • The NI 7932R with a Xilinx Kintex-7 325T FPGA and two SFP+ optical transceiver cages
  • The NI 7935R with a Xilinx Kintex-7 410T FPGA and two SFP+ optical transceiver cages


Physically, all three controllers look very similar:



NI Controller for FlexRIO.jpg



These three controllers accept any one of more than 30 of NI’s FlexRIO Adapter Modules, encompassing analog input ports with digitizing speeds to 3Gsamples/sec, analog output ports with output rates as fast as 2Gsamples/sec, digital I/O with individual line rates as fast as 1Gbits/sec, RF Rx/Tx channels with frequencies reaching 4.4GHz, a video-camera-specific Camera Link module, and a customizable adapter kit for roll-your-own I/O.


The controllers’ integrated Zynq SoC implements many of the controllers’ I/O ports (Ethernet, USB, etc.) and executes LabVIEW-generated code. The Zynq SoC’s internal FPGA provides controller housekeeping functions and implements an AXI tunnel port that connects to the paired Kintex-7 FPGA. The IP for the AXI tunnel also came from Xilinx. The Kintex-7 FPGAs in the controllers implement the adapter-module-specific interface protocols and execute LabVIEW-generated, hardware-accelerated processing tasks. There’s 2Gbytes of SDRAM connected to the FPGA to hold large data sets. This capability comes in handy for tasks such as processing long FFTs, for example.




About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.