Back when Keysight Technologies was Agilent, I wrote about the company’s EEsof EDA W1462 SystemVue FPGA Architect that let you design with, simulate, and program the FPGAs on the Agilent M9703A AXIe wideband digital receiver/digitizer. Now I can write about the next step: Keysight’s U5340A FPGA development kit, which lets you develop and deploy high-speed signal processing algorithms in the FPGAs incorporated into the company’s full range of high-speed PCIe digitizers and its 12-bit AXIe 8-channel wideband digital receiver/digitizer. Capabilities of these digitizers range from 8 to 12 bits and 100Msamples/sec to 8Gsamples/sec.
The Keysight U5340A FPGA Development Kit lets you configure the custom real-time processing area of the FPGA that resides within each Keysight high-speed digitizer (shown below) using Keysight IP cores to connect your custom real-time processing logic to the surrounding board resources.
Because this is the Xcell Daily blog, you will not be surprised to learn that those FPGAs are from Xilinx and that the Keysight FPGA Development Kit uses Xilinx development tools as a foundation technology. The FPGA Development Kit runs on a Windows PC, interacts with two embedded engines from Mentor Graphics and Xilinx, and communicates with the FPGA in the digitizer module. The embedded Mentor Graphics engine supports algorithm design, synthesis, simulation and validation. The embedded Xilinx engine fits your design into the FPGA and provides debug and in-FPGA logic analyzer capabilities. Unsurprisingly, Keysight’s high-speed digitizer R&D team makes use of these same tools.
Xilinx has announced that the SDAccel development environment for OpenCL, C, and C++ now complies with the Khronos OpenCL 1.0 standard. SDAccel creates a software-centric way to use programmable logic for application acceleration by combining the industry's first architecturally optimizing compiler for FPGAs supporting OpenCL, C, and C++ kernels with libraries, development boards, and a CPU/GPU-like development and run-time experience.
"Now the entire OpenCL design community can seamlessly take advantage of Xilinx FPGAs" said Neil Trevett, president of the Khronos Group and chair of the OpenCL working group.
For an SDAccel backgrounder, click here.
Meanwhile, here’s a 5-minute introduction to SDAccel from Xilinx CTO Ivo Bolsens:
I wrote about the FPGA-based Saleae Logic Pro 8 late last year. It’s a tiny 8-channel logic analyzer/DSO that interfaces to a PC using a USB 2.0 cable. It measures just over two inches (53mm) on a side and is less than half an inch (12mm) thick and is based on a Xilinx Spartan-6 LX16 FPGA. Well, Saleae sent one of these units to my good friend, embedded-design expert, and embedded.com columnist Jack Ganssle and he’s written a pretty positive review of the product. Here are a few excerpts from his embedded.com review:
“Unlike most USB instruments, the thing is beautiful, solid, and even comes in a zip-up traveling case, though is so small a shirt pocket could hold it plus the requisite pocket protector.”
“The Logic Pro 8 doesn’t have any analog triggering modes so isn’t quite an MSO. However, it can gather so much data (limited by the memory in your host computer) that in most cases this will not be much of a limitation.”
“I really like the 12-bit A/Ds and +/- 10V input range. I found voltage readings accurate to about 0.1%, an astonishing number for a scope.”
“You could set up a development lab on an airplane’s tray! I suspect the flight attendants wouldn’t be too thrilled.”
“This might be the fastest USB instrument UI I’ve used.”
Click here for Jack’s full review.
Now that many Xilinx All Programmable devices including most members of the 20nm Virtex UltraScale device family and the Virtex-7 580T and 870T devices can operate quite reliably at transceiver rates in excess of 28Gbps, you’re going to want to know how to design pc boards that support these extreme line rates. Keysight wants to tell you how to do this with a free Webinar on January 22. That’s tomorrow!
If you’re involved in the design of small cells or other sorts of low-power RF applications including telecommunications, wideband tactical radio, and radar, then you’ll be interested in a new White Paper from Cree. The White Paper describes a GaN PA (power amplifier) based on the Doherty architecture that delivers excellent RF power efficiency using an asymmetric structure to permit higher back-off levels while still meeting spectral limit requirements. CFR (crest factor reduction) and DPD (digital pre distortion) algorithms along with DUC (digital up conversion) and DDC (digital down conversion) implemented as IP blocks within the programmable logic of a Xilinx Zynq SoC are responsible for achieving these results from a Doherty PA.
If you’re interested in a more complete description of these results with hard data, then click here to get a copy of the White Paper “GaN PA Supports 3.5-3.7 GHz Small Cell Applications Using Digital Predistortion” from the IEEE Communications Society and Cree.
By Adam Taylor
In the previous instalment of this series, we reached the point where we could run the example and gain profiling data for analysis. Running the profiler generates a gmon.out file, which contains the profiling data. This file is generated when the application program terminates naturally or when the application is terminated via the SDK interface.Read more...
Artist concept showing the Dawn spacecraft with Ceres
Image credit: NASA/JPL-Caltech
NASA’s Dawn spacecraft, launched in late 2007, is approaching the dwarf planet Ceres in the Solar System’s asteroid belt and just sent back a short video (shown below). Ceres orbits the sun at an average of 2.77 AU. (An AU is 149.6 million km so 2.77 AU is a little more than 400 million km.)
The Dawn spacecraft observed Ceres for an hour on Jan. 13, 2015, from a distance of 238,000 miles (383,000 kilometers). A little more than half of its surface was observed at a resolution of 27 pixels. This animated GIF shows bright and dark features.
Image Credit: NASA/JPL-Caltech/UCLA/MPS/DLR/IDA/PSI
The images in this video were captured by the Dawn spacecraft’s Framing Camera, a multi-talented refractive telescope with a 1024x1024-pixel CCD imager capped with an electronic shutter. There are two identical Framing Cameras in the spacecraft for redundancy and each camera is controlled by its own FPGA-based DPU (data processing unit) developed at IDA (the Institut für Datentechnik und Kommunikationsnetze at TU Braunschweig) in Germany.
A space-grade, radiation-tolerant 90nm Xilinx Virtex-4QV FPGA implements the Framing Cameras’ major DPU functions including:
The weekend mail brought a padded envelope containing two 3rd-generation miniSpartan6+ development boards from Scarab Hardware. Visually, the boards are very nearly identical. They differ only in the Spartan-6 FPGA mounted on the board. One of the two boards I received has a Spartan-6 LX9 FPGA and the other has a Spartan-6 LX25 FPGA. Here’s a comparison table:
As you can see from the above table, the Spartan-6 LX25 device has more than double the on-chip logic resources, nearly three times the number of flip-flops (that’s a lot of additional state), nearly double the on-chip distributed RAM and BRAM, and more than twice as many DSP48A1 slices—substantially more resources across the board.
The LX9 version of the Scarab Hardware miniSpartan6+ board now costs $75 (only $6 more than the discounted Kickstarter funding price of $69) and the LX25 version is $105, only $30 additional. For me, it was a no-brainer; I ordered the board with the larger FPGA. This is possible because of the pin compatibility between the Spartan-6 LX9 and LX25 FPGAs in the FTG256 fine-pitch BGA package. (For more Xcell Daily discussions of FPGA pin compatibility and product design, see “How to overcome product obsolescence and inject a mid-life kicker using pin-compatible FPGAs—A quick, real-world case study” and “New UltraScale FPGA pinout guide shows you how you can design one pcb that takes six different devices.”)
What Scarab Hardware means when it calls this miniSpartan6+ board a 3rd-generation design is that the company made some substantial improvements to the original Kickstarter project proposal. Even so, the resulting board design is still significantly smaller than a plastic credit card, but it sports a long list of product features. In addition to the Xilinx FPGA, the miniSpartan6+ gives you:
That’s a lot of resources to play with. You really ought to be able to do something interesting with this board.
Given the old saying that a picture is worth 1K words, here’s an annotated photo I shot this morning of my LX25 miniSpartan6+:
As you can see, this is a very capable design for learning about FPGAs. However, the board is not just a learning tool in my opinion. It can certainly form the basis of a production product given the substantial amount of I/O available on the headers and the standoff holes located in the board’s corners that would add mechanical strength to a product assembly.
In addition to the downloadable Xilinx ISE Design Suite tools for the Spartan-6 family, Scarab Hardware is developing a Mojo-based development IDE for the miniSpartan6+ board. You’ll find the latest version of the Scarab IDE here.
For earlier Xcell Daily blogs about the Scarab Hardware miniSpartan6+ board that I wrote when the board was a Kickstarter project, see:
The ancient VMEbus has its roots in the 32-bit VERSAbus, developed by Jack Kister at Motorola’s Semiconductor Products Group for the 68000 microprocessor in the 1970s. VME is an abbreviation for Versa Module Europe, which ditched the VERSAbus’ card-edge connector for more reliable DIN connectors. The first 32-bit VME boards started to appear in the early 1980s and by 1994, the VMEbus had evolved into VME64, which became an extremely successful, open-architecture bus specification operated under the auspices of the VMEbus Manufacturers Group, now known as VITA. The longevity of the VMEbus and VITA’s efforts to maintain and upgrade VME standards as electronics technology advanced resulted in a large number of VME board designs over the decades. Fast forward to the 21st century and you find that PCIe is very much the bus of choice thanks to immense success in the PC arena. IOxOS Technologies—an electronic design company specializing in the aerospace, physics, and telecommunications industries—is now offering a well-proven PCIe-to-VME bridge IP block as a pre-built, encrypted binary configuration file that’s ready to drop into a Xilinx Artix-7 FPGA.
The IOxOS Technologies ALTHEA 7910 PCI Express to VME64x bridge IP core has been successfully implemented and validated in all of the company’s VME SBCs (single-board computers) since 2009 and has been used with many processors including Intel x86 (Xeon, i5/i7), AMD (Opteron), and PowerPC (QorIQ P and T series) platforms running under Microsoft’s Windows XP and Windows 7, Linux, and Wind River’s VxWorks. This IP core provides you with a low-latency, high-bandwidth bridge to a PCIe upstream port with full VME64x Master/Slave interface, Slot-1 functions, and interrupt management. Here’s a block diagram of the ALTHEA 7910 core:
You may not need a PCIe-to-VMEbus64 bridge but the IOxOS Technologies ALTHEA 7910 PCI Express to VME64x bridge IP core illustrates a solution to a much bigger problem that involves bridging the past to the present and the future. FPGAs excel at bridging because they’re fast, flexible, and have high I/O pin counts. You need all three for bridging functions.
Take a close look at the IOxOS Technologies ALTHEA 7910 block diagram above. In addition to relatively simple bridging, there are additional functions added including a quartet of DMA engines, a DDR3 SDRAM controller, and power-supply and temperature monitoring. These functions boost performance, improve system reliability, and are often needed or at least handy for adapting older designs to present needs. The IOxOS core fits in an Artix-7 XC7A75T FPGA, which is a mid-sized member of the 7 series Artix-7 low-end FPGA family. Because it’s based on an advanced, low-power TSMC 28nm HPL IC process technology, Xilinx Artix-7 All Programmable devices can implement bridging functions with low power requirements. The IOxOS Technologies ALTHEA 7910 IP core implemented in an Artix-7 XC7A75T FPGA consumes less than 1.5W.
If you are tasked with getting an image from sensor to system, you know this is not an easy process. Most likely, you’ll employ some sort of image-signal-processing (ISP) pipeline. These pipelines can be remarkably complex. Xylon offers a pre-built ISP pipeline for Xilinx 7 series All Programmable devices—the logiISP Image Signal Processing (ISP) Pipeline—and it’s available for evaluation as a free reference design for the Zynq-based MicroZed Embedded Vision Development Kit from Avnet Electronics Marketing. The logiISP IP core accepts various video formats generated by different sensors with spatial resolutions to 7680x7680 pixels including 1080p60 (1920x1080@60fps), and removes defective pixels, de-mosaics Bayer-encoded video, makes image color and gamma corrections, filters noise from the video, collects video analytics data for various control algorithms, and manipulates video data formats and color domains.
The logiISP core can be used with processor-based control algorithms for Auto White Balancing (AWB) and Auto Exposure (AE) that work with the video analytics data collected by the ISP pipeline. The AXI4-compliant logiISP core is prepackaged for Xilinx Vivado IP Integrator (IPI) tool and requires no special skills beyond general tools knowledge. You use it in the same way as any other Xilinx IP core.
Here’s a block diagram of the logiISP Image Signal Processing (ISP) Pipeline:
You can now access the free, on-demand IEE tutorial “Minimize Development Effort for Complex Wireless Applications Integrating both Hardware and Software on the Zynq All Programmable SoC” on the IEEE Communications Society’s Web site (registration required). Created by Carl Cao, PhD, Wireless System Architect and Yuan Gu, Senior Business Manager at Xilinx, this tutorial provides detailed explanations on topics such as:
Using an all-in-one radio DFE (digital front end) as an example, this tutorial demonstrates the abilities of the Xilinx family of Zynq All Programmable SoCs to support complex carrier-grade, high-performance, and low-cost wireless applications.
Click here to register and get instant access to the Webinar.
IP for face tracking would seem to have broader application than you might think on – ahem – face value. Yet Xylon’s logiREF-FACE-TRACK-EVK Face Detection and Tracking IP block has been the most popular IP on the Design & Reuse Web site for the last three weeks. Here’s a demo of the IP optimized for and running on a Zynq SoC:
What can you use this IP for? Xylon’s logiREF-FACE-TRACK-EVK Face Detection and Tracking Web page lists:
There’s a logiREF-FACE-TRACK-EVK reference design that allows you to quickly evaluate and experiment with Xylon's face detection and tracking solution on the MicroZed Embedded Vision Development Kit from Avnet Electronics Marketing. This free and pre-verified design includes evaluation logicBRICKS IP cores and hardware design files prepared for the Xilinx Vivado Design Suite.
As it happens, face tracking popped into the news today in an unrelated story about the New Nintendo 3DS XL handheld gaming system that launches early next month. The VentureBeat article “New Nintendo 3DS XL impressions: Face-tracking fixes the handheld’s biggest problem” says “It may have taken four years, but Nintendo looks to have finally fixed the biggest problem with the 3DS: the 3D… One of the biggest changes to the 3DS system is almost invisible, but its inclusion makes a notable difference when it comes to gameplay. A secondary camera was added to the system to enable face-tracking. This enables the New 3DS to adjust the top screen’s image to the player’s viewing angle by tracking the player’s eyes, dynamically adjusting the 3D sweet spot on the fly. Internal hardware does the tracking, which means that even legacy games benefit from this.”
Note: I do not mean to imply here that the face tracking built into the New Nintendo 3DS XL handheld gaming system is based on Xylon IP or on Xilinx All Programmable devices. I’m merely illustrating yet another interesting application for face-tracking technology in an end product that’s going to cost about $200 in the hope that this example might give you some ideas for using face tracking in your own system designs.
Xilinx has shipped the first copies of the 20nm Virtex UltraScale VU440 All Programmable device. Dig these specs:
This thing is enormous—thanks to 3D IC technology—and it adheres to the SoC and ASIC prototyping mantra: “You can’t be too thin, too rich, or have too many gates.”
Seeing is believing, so here’s a video of one of these devices in action, implementing ten instances of an ARM Cortex-A9 32-bit RISC CPU on one Virtex UltraScale VU440 device with some incredible utilization stats for such a large device:
All ten instances of the ARM Cortex-A9 CPU meet timing and run at 50MHz. That’s a real testament to the Vivado Design Suite’s ability to handle extremely large designs.
Here’s the video:
Hot on the heels of yesterday’s blog post about UltraScale device pin compatibility comes this related story. EEVblog proprietor Dave Jones regularly tears down new and old electronic products and then discusses how they’re designed. This week, Dave tore down a newly introduced Keysight InfiniiVision 3000T X-Series digital mixed-signal oscilloscope. (See Dave’s 12-minute teardown video here.) This new scope is based on the model 3000A scope, introduced and reviewed back in early 2011 back when Keysight was called Agilent. Four years later, the newly introduced version of this product sports several significant new features. For the purpose of this blog, the important new features are a capacitive touch screen, graphical zone triggering (borrowed from the company’s 4000-series scopes), and integrated DSP/math waveform processing—but there are many other new features as well.
When Dave cracks open the Keysight 3000T scope in this week’s teardown video, he finds that very little of the hardware design has changed from the 3000A scope he tore down four years ago. The 3000T motherboard has a new interface port for the capacitive touch screen and, initially, that’s the only difference that Dave can see. A significant portion of the scope’s abilities come from the proprietary Keysight MegaZoom ASIC, specifically designed for the 2000 and 3000 X-Series scope families and that ASIC is reused on the 3000T motherboard. However, on closer inspection of the main board in the 3000T, Dave notes that there’s a different FPGA on the main pc board. The FPGA’s package is just different enough to notice the change.
The original 3000A scope used a Xilinx Spartan-3 XC3S1200E FPGA and the new 3000T scope uses a larger Spartan-3 XC3S1600E FPGA instead. The larger Spartan-3E device delivers 70% more logic, nearly 30% more BRAM, and more multipliers than the smaller FPGA. Yet Keysight is able to add these significant resources to the system design, deriving some interesting system-level benefits and competitive product advantages from these additions, without significant pc board changes even though four years have elapsed since the initial design of the 3000A scope.
Keysight realized significant product-level benefits from the FPGA upgrade for two important reasons. First, there’s the pin compatibility. There are three Spartan-3E FPGAs available in the same FG320 fine-pitch BGA package and the XC3S1200E and XC3S1600E devices have identical I/O resources as shown in the image below, taken from the latest version of the DS312 Spartan-3E Product Specification.
Second, the 90nm Spartan-3E family is still available. The family was announced ten years ago in 2005.
This is a concrete example of the risk reduction and future-proofing you get when you incorporate Xilinx FPGAs into your system design. Although you may have heard the words before, this example of the upgraded Keysight 3000T X-Series DSO/MSO illustrates that these ideas are more than just words. Pin compatibility and Xilinx device family longevity are significant factors in reducing design risk.
As mentioned earlier this week, the pin-compatible alternatives available in the new Xilinx 20nm UltraScale FPGAs are even more extensive, as shown in the chart below:
Depending on how many I/O pins your design requires, you can get anywhere from two to six pin-compatible choices. In the case of the B1760 and B2104 UltraScale packages, you can choose from six different Virtex UltraScale and Kintex UltraScale All Programmable devices with a wide range of on-chip resources. It’s certainly something you’ll want to consider for your next system design. Download the new User Guide, UG575, “UltraScale Device Packaging and Pinouts,” here.
It’s no small feat to create a wide range of pin-compatible All Programmable FPGAs, especially at the stratospheric resource and performance levels of the new 20nm Xilinx Virtex and Kintex UltraScale devices. However, there are actually two pinouts, one with 1760 connections and one with 2104 connections, that will accept six different UltraScale devices each. There's a new User Guide, UG575, pragmatically titled “UltraScale Device Packaging and Pinouts” that describes this. You can download a PDF here, but here’s a table from the User Guide that shows the pin compatibility of the Virtex and Kintex UltraScale devices:
There are I/O differences, so the User Guide goes into greater detail including a Captain Midnight secret decoder ring for bank numbering differences from one device to the next. If you’re planning on designing a board or boards that use multiple UltraScale devices depending on the board’s use, then you’ll want to download a copy of this guide.
There are more than a dozen operating systems and RTOS choices for the Zynq SoC. One of those is OSE from Enea. OSE is a POSIX-compatible, multicore RTOS with deep roots in the telecom industry. However, OSE offers plenty of features for any industry including predictable performance, fault tolerance, advanced networking and security features, and IP stacks. Best of all in the context of this blog post, there’s a Zynq-specific version of OSE that runs on the Zynq SoC’s dual-core ARM Cortex-A9 MPCore processor available from Enea and you can get a no-charge, 30-day evaluation copy. Just click here for more information.
Here's a block diagram showing you how OSE is organized:
If you are new to the idea of muticore RTOSes, you might want to also download a copy of the Enea White Paper titled “Fundamentals of Multicore: Operating Systems for Telecom/Networking Applications.”
By Adam Taylor
In the previous blog in this series, we looked at the use of XMD and XSDB to debug our applications and systems. Another very important aspect of ensuring that our application is optimized for performance is the ability to profile it.
Profiling is different than debugging. For profiling, we modify the code to use the SCU timer and its interrupt to sample and store the application state at fixed intervals, which allows us to determine the functions that are called most often and the elapsed time during the execution of each function call. Knowing this information helps us reduce code bottlenecks and ensure that the system performs as required.
Yesterday at CES, intoPIX received a Technology and Engineering Emmy award in the “Standardization and Productization” category from the National Academy of Television Arts & Sciences for its interoperability work related to transporting video using the JPEG2000 Broadcast Profile over in MPEG-2 TS over IP networks. The award recognizes intoPIX and several other technology companies in the Video Services Forum (VSF). Here’s a photo of Katty Van Mele, intoPIX Director of Business Development, accepting the Emmy:
Gael Rouvroy, CTO and founder of intoPIX said, “We are proud to be honored with this award along with our colleagues in the VSF for our work in the development of TR-01 J2K interoperability recommendations. This recognition further validates our pioneering work in developing best-in-class video compression solutions for migrating Broadcast and Pro-AV industries to an IP future based ecosystem.”
intoPIX JPEG2000 IP cores include HD and Cinema encoders and decoders, lossless encoders and decoders, UHD 4K/8K encoders and decoders, and J2K-RAW encoders and decoders. Versions of all intoPIX JPEG2000 encoders and decoders are available for Xilinx 7 series All Programmable devices—Virtex-7, Kintex-7, and Artix-7 FPGAs and Zynq SoCs. Some of the intoPIX JPEG2000 IP cores are also available for Virtex-6, Spartan-6, and Virtex-5 devices.
The new Avnet WiLink 8 Adaptor card couples the Texas Instrument WL1835MODCOM8 (2.4 GHz) or WL1837MODCOM8I (5.0 GHz) wireless evaluation boards to the Avnet Zed series of Zynq-based eval cards (ZedBoard, MicroZed, PicoZed, and Mini Module Plus) through two PMOD ports. Documentation and example designs demonstrate the software build process using Yocto and Xilinx’s Open Source Linux Distribution. Details on how to add Wi-Fi, Bluetooth and BLE are covered in detail, helping developers quickly add wireless capabilities for Internet of Things, multimedia, industrial and home automation, security, and M@M industrial applications.
Yesterday at CES, Barco Silex accepted a Technology and Engineering Emmy award in the “Standardization and Productization of JPEG2000 Interoperability” category from the National Academy of Television Arts & Sciences. The award recognizes Barco Silex and several other technology companies in the Video Services Forum (VSF) for their work on the advancement of interoperability for JPEG2000 video-compression systems. The presentation ceremony occurred at the Bellagio Hotel in Las Vegas during CES but Barco Silex actually tweeted news of the award last August.
The Barco Silex video team was led by Jean-Marie Cloquet, the company’s Image Processing Division Manager, who played a key role in the VSF J2K Activity Group, culminating in the release of a Technical Recommendation for “Transport of JPEG2000 broadcast profile video in MPEG-2 TS over IP” in April, 2014.
Barco Silex has a large JPEG 2000 portfolio including this compact real-time hardware decoder engine that is optimized for Digital Cinema (DCI) and High-Definition (HD) video applications. The company’s BA109 JPEG2000 decoder IP is able to sustain the high decoding requirements of the large DCI frame formats, including 4096x2160 resolution and frame rates up to 48 frames per second. Its BA110 JPEG2000 encoder IP core, dedicated to DCI (Digital Cinema Initiatives) and HD video applications, encodes large un-tiled color frames with 4:4:4 or 4:2:2 sub-sampling. The BA110 generates compressed streams compliant with the ISO/IEC 15444-1 specification (JPEG 2000).
Late last year, National Instruments (NI) announced that its co-founder, president, and CEO Dr. James Truchard (popularly known by nearly everyone as “Dr. T”) has been named an IEEE Fellow for outstanding leadership and achievement in technology. Dr. Truchard pioneered and championed the idea of computer- and PC-based instrumentation starting with the creation of an IEEE-488 interface board for DEC PDP-11 minicomputers in 1976—six years after the PDP-11’s introduction—and continuing with PCs in 1983—two years after the introduction of the original IBM PC. The company’s groundbreaking LabVIEW graphical programming language appeared in 1986. It originally ran on the Apple Macintosh but quickly moved to Microsoft Windows.
Since then, NI has built a huge and faithful following by developing ways to make instrumentation faster and easier to program. One of those ways is LabVIEW FPGA, which serves as a bridge between LabVIEW programmers and the Xilinx FPGAs and Zynq SoCs embedded in many NI hardware products. (See “How Xilinx All Programmable technology has fundamentally changed business at National Instruments.”)
Dr. James Truchard, co-founder, president, and CEO of National Instruments
Dr. T has also made education, especially technology education, a fundamental part of National Instruments both inside of the company and in the broader community. Last year, NI won the STEM Education Impact Award at EELive! 2014 for:
Congratulations, Dr. T! A well-deserved honor.
See the EETimes article “NI's Truchard Named IEEE Fellow” for more detail about Dr. T’s IEEE Fellow award.
For more information about LabVIEW FPGA and other FPGA-based NI products, see:
The $69.97 Hackaday Arduino-compatible Spartan-6 FPGA Shield adds “FPGA awesome-ness” to the popular, open-source Arduino embedded platform. The board incorporates a Xilinx Spartan-6 LX9 FPGA in an Arduino Shield form factor. Both the Arduino and the FPGA benefit from this combination. The Arduino can program the SPI Flash configuration memory on the FPGA board and the Xilinx Spartan-6 FPGA adds fire-breathing hardware performance to the 8-bit AVR microcontroller on the Arduino board. You can also program the Shield using the on-board JTAG programming pins and you can use the low-cost board without an Arduino if you like.Read more...
The latest version of the Xilinx Software Development Kit (SDK), included with the Vivado Design Suite and available as a separate free download, has been enhanced with a System Performance Analysis (SPA) toolbox that aids early exploration of hardware and software systems based on processor-based devices such as the Zynq-7000 All Programmable SoC. These explorations give you—the system designer—insights into the data-flow interactions between the two ARM Cortex-A9 MPCore processors in the Zynq SoC’s PS (processor system) and hardware blocks implemented in its PL (programmable logic). The Xilinx SPA toolbox gives you the tools you need to model and observe system performance at critical stages of your design, even the earliest stages, so that you can optimize your system’s performance repeatedly during the design process.Read more...
Luke Miller recently published a blog on SemiWiki.com titled “Is Your FPGA Design Secure? Use Xilinx to Make Sure.” With the amount of recent press coverage connected to Internet-based hacking and other data breakins, the need for more secure system designs ought to be self-evident.
Miller’s blog post contains several pointers to Xilinx resources that will indeed help you beef up your design’s security. Miller recommends that you start at the Design Security Solutions page on the Xilinx Web site. There, you’ll see this chart listing the various active and passive security features in the latest four All Programmable device generations (UltraScale, 7 series including the Zynq SoC, Virtex-6 and Spartan-6, and Virtex-5).
Miller also suggests you look at three additional Xilinx documents:
All very good advice.
Last month, National Instruments (NI) introduced the LabVIEW Communications System Design Suite, which combines software defined radio (SDR) hardware with a comprehensive, unified software design flow to help engineers prototype 5G systems. The package includes built-in application frameworks for WiFi and LTE that enable wireless developers to focus on creating specific components based on existing standards rather than designing new algorithms from scratch. It allows people to rapidly combine new communications concepts with real-world I/O. “For some of the academic and industry researchers in our lead user program, this approach has cut the time to a validated prototype in half” said James Kimery, director of RF and Communications at NI.
The LabView Communications System Design software is coupled with the company’s USRP software-defined radio development platform for 5G research, which is based on a Xilinx Kintex-7 All Programmable device. (See “Software-defined radio dev platform for 5G research handles MIMO, massive MIMO using Kintex-7 FPGA.”) Wireless engineers can use the NI USRP RIO and the NI LabVIEW Communications System Design software to rapidly prototype real-time wireless communications systems and test them under real-world conditions. You can explore more complex, more capable wireless algorithms and develop systems faster because the LabVIEW graphical system design and programming environment allows you to focus on solving actual wireless communications problems instead of being concerned with underlying implementation details.
LabVIEW Communications provides a single, cohesive environment that enables users to program both processors and FPGAs. LabVIEW Communications supports a variety of design languages and approaches including C, .m, and NI’s G dataflow language. The graphical dataflow language is able to span both processor and FPGA execution hardware seamlessly. (For more detailed information, see “Software Synthesis from Dataflow Models for G and LabVIEW.”) LabVIEW Communications also provides built-in tools for data-driven float-to-fixed point conversion to ensure a seamless transition of algorithms designed in G between processor and FPGA hardware.
Monrovia Microsystems’ Multitarget Development System (MDS) for Xilinx PicoBlaze soft-core processors is a graphical integrated development environment (IDE) that normally costs 349€. Until the end of this month (January, 2015), the premium commercial license is 60€, the basic commercial license is 40€, and the non-commercial premium license costs $10€. MDS provides all you need to develop software for PicoBlaze applications: source code editor, assembler, disassembler, and simulator. It's available in a Microsoft Windows version and a GNU/Linux version for x86 machines.
The PicoBlaze soft-core processor is a resource-efficient (as small as 26 slices!), fully embedded 8-bit RISC microcontroller core with predictable interrupt response times that’s optimized for Xilinx programmable logic—including the latest UltraScale and Zynq SoC All Programmable devices and backwards in time to nearly the beginning of the FPGA era. With its predictable performance and high speed—always two clock cycles per instruction with a clock rate as fast as 240MHz in newer Xilinx devices—the PicoBlaze processor is an ideal implementation vehicle for complex state machines within a larger FPGA-based system design. It’s also tiny enough to permit the use of multiple processor instances in the same design.
Key features of Monrovia Microsystems’ MDS include:
Still not convinced? There’s a free trial version to download as well.
A big part of the ever-present “go-faster” imperative is getting more bits per second through the same number of pins. Nowhere is that imperative more evident than OpenVPX Gen3 signaling, which Curtis-Wright has realized with its Fabric40 Technology Program to allow its customers to implement 10Gbps and 40Gbps Ethernet (40GbE) or QDR Infiniband communications fabrics over OpenVPX backplanes and cables originally designed for a much lower 6.25Gbps operation. The company’s Fabric40 Program establishes the industry’s first complete end-to-end approach to integrating the latest high-speed fabrics into customer applications. In addition to enabling individual system components with 40Gbps high-speed interconnects, the Fabric40 Program also ensures that all aspects of this new data fabric technology are optimally configured to work together, which greatly reduces our customers’ integration risks and development time. According to Curtis-Wright, the Fabric40 technology delivers 40-100% greater eye height with improved BER and better margin.Read more...
By Adam Taylor
The last MicroZed Chronicles blog looked at two methods of communicating with the XADC using the Zynq SoC’s AXI or DevC interfaces. I demonstrated the two XADC communication methods by outputting to the XADC base address in each driver. The code in this approach booted from an SD Card so that I could be sure that the application was capable of being deployed standalone.
We can take another approach to verify the access method and addresses: we can use one of the two debuggers present within the Xilinx SDK:
Yesterday, Xilinx announced that its 20nm Kintex UltraScale KU040 FPGA had moved to production status. This is the first Xilinx All Programmable 20nm device—indeed the industry’s first 20nm programmable logic device—to go into full production. The 20nm Kintex UltraScale KU040 FPGA incorporates 424,200 logic cells, 21.1Mbits of BRAM (Block RAM), 1920 DSP48E2 slices (see “The UltraScale DSP48E2: More DSP in every slice”), three PCIe Gen3/Gen4 hardened and integrated IP cores, 20 GTH 16Gbps SerDes transceivers, and 520 I/O pins.
Even though it’s the second smallest member of the Kintex UltraScale FPGA family, the 20nm Kintex UltraScale KU040 FPGA offers systems designers more on-chip resources than most of the members of the extremely successful Xilinx Kintex-7 FPGA family at significant power savings relative to the 7 series generation. The largest member of the Kintex UltraScale FPGA family, the KU115, offers roughly three times the number of on-chip resources: 1,160,880 logic cells; 75.9Mbits of BRAM; 5520 DSP slices; 6 PCIe IP blocks; and 64 GTH SerDes transceivers.Read more...