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Xilinx Vivado Design Suite 2015.2 now ready for download

by Xilinx Employee ‎07-01-2015 10:29 AM - edited ‎07-01-2015 10:50 AM (370 Views)

The latest version of the Xilinx Vivado Design Suite—version 2015.2—is now ready for download. This release includes improvements in Partial Reconfiguration, Tandem Configuration, and the Vivado implementation tools. It also includes support for the Virtex UltraScale XCVU160 and Kintex UltraScale XCKU060 FPGAs and the hi-reliability Virtex-7 XQ7VX690T FPGA and Zynq XQ7Z045 and XQ7Z100 SoCs. More information in the release notes.

 

Download Xilinx Vivado Design Suite 2015.2 here.

 

We have Tapeout! Xilinx Zynq UltraScale+ MPSoC ready for TSMC’s 16FF+ process

by Xilinx Employee ‎07-01-2015 10:07 AM - edited ‎07-01-2015 03:29 PM (420 Views)

Today, Xilinx announced the successful tapeout of the first heterogeneous, multicore, All Programmable Zynq UltraScale+ MPSoC—now ready for fabrication using TSMC’s 16nm 16FF+ FinFET process technology. I apologize for those many adjectives—but as you’ll see below, they’re all needed.

 

Like the original Xilinx Zynq SoC, the Xilinx Zynq UltraScale+ MPSoC combines multiple hardened ARM processor cores with Xilinx programmable logic to produce an enhanced application processor that can tackle a broad range of high-performance tasks that cannot be achieved using software alone using on-chip, FPGA-boosted hardware accelerators.

 

The Xilinx Zynq UltraScale+ MPSoC simply has a lot more of everything including:

 

  • Quad-core, 64/32-bit ARM Cortex-A53 processor for immense application-processing power
  • Dual-core, 32-bit ARM Cortex-R5 processor for real-time and safety-critical software execution
  • ARM Mali-400 MP GPU for implementing high-performance graphics, offloading these tasks from the on-chip ARM Cortex-A53 CPUs and the ARM Cortex-R5 real-time processors
  • A hardened H.265/264 Video Codec Unit that provides native UltraHD compression
  • Dedicated Security Processing Unit with multiple military-class security protocols to prevent any conceivable unauthorized access
  • Hardened, integrated SDRAM memory controller supporting DDR4, LPDDR4, DDR3, DDR3L, and LPDDR3 memory devices
  • Large arrays of Xilinx UltraScale+ programmable logic including the new, larger embedded UltraRAM blocks; a large number of UltraScale DSP48E2 slices; and hardened, integrated PCIe Gen2/Gen3/Gen4 and 100G Ethernet blocks
  • Xilinx programmable I/O that can handle anything from simple logic pins to high-speed PCIe and 100G+ Ethernet serial protocols

 

Zynq UltraScale+ MPSoC Block Diagram.jpg

 

 

Zynq UltraScale+ MPSoC Family Block Diagram

 

 

 

Clearly, these new Zynq UltraScale+ MPSoC devices are not destined for smart toasters. So where are they headed?

 

They’re going into the most performance-intensive embedded systems on the planet. Some of the targeted applications, well-suited to the Zynq UltraScale+ MPSoC’s substantial processing and real-time capabilities, include:

 

 

 

 

 

So you have an embedded design all coded up for one microprocessor architecture and you’d love to take advantage of the significant additional processing power of the dual-core ARM Cortex-A9 MPCore processor/programmable logic combination available with the Xilinx Zynq SoC? Want some help porting that code?

 

Help is available with the new “Zynq-7000 All Programmable SoC Architecture Porting Guide,” UG1181. Following a quick overview of the ARM Cortex-A9 processor features found in the Zynq PS (Processor System), the guide gives the following handy table highlighting the differences among five processor architectures including the ARMv7 architecture, PowerPC, MIPS, Renesas-SH, and x86:

 

 

Processor Architecture Comparison.jpg

 

 

The document also includes a comparison of function-calling conventions, interrupt models, memory maps, register sets, and pointers to the ARM Web pages that provide detailed help in porting from these other processor architectures.

Many distributed networks including those used for 5G communications, power-grid monitoring, and particle physics research need precise time synchronization among the distributed network nodes. CERN’s White Rabbit Ethernet protocol is designed to provide sub-nanosecond accuracy while synchronizing more than 1000 network nodes connected via either fiber or copper. As reported at a status update meeting a week ago, the EN-ICE group in CERN’s Engineering Department has developed a plug-in White Rabbit module for National Instrument’s CompactRIO (cRIO) control and monitoring system based on a low-end Xilinx Spartan-6 FPGA. Here’s an annotated photo of the board:

 

 

CERN White Rabbit Module for NI cRIO.jpg

 

 

The module connects to the network via its optical SFP port and generates disciplined reference clocks that are used by the rest of the local node for network timing synchronization. With the Spartan-6 FPGA clocking at 160MHz, no output clock jitter was detected in the latest design tests.

 

 

Prior Xcell Daily coverage of CERN’s White Rabbit protocol:

 

 

China Mobile Research Institute (CMRI) and Xilinx have just signed an MOU for development of the Next Generation Fronthaul Interface (NGFI) to be used in C-RANs (Cloud-based Radio Area Networks), RRUs (Remote Radio Units), large-scale antenna systems, 3D MIMO (multiple-input, multiple-output) antenna systems, and other 5G infrastructure components. Where does NGFI fit in a C-RAN network architecture? Here’s a block diagram to illustrate, taken from CMRI’s NGFI White Paper:

 

 

CMRI C-RAN Architecture with NGFI.jpg

 

 

As the above figure shows, NGFI is the fronthaul interface between baseband processors and remote radio heads in the radio network infrastructure. NGFI shifts some BBU (baseband unit) processing functions to the RRUs, which alters BBU and RRU architecture. As a result, this next-generation architecture redefines the BBU as the Radio Cloud Center (RCC). Collections of RRUs, possibly managed by Radio Access Units (RAUs), become Radio Remote Systems (RRS). In addition, the existing fronthaul protocol using point-to-point connections morphs into a many-to-many fronthaul network that employs a packet-exchange protocol.

 

NGFI is a work in progress. Xilinx is contributing a validated NGFI reference design based on the Zynq SoC to the NGFI R&D effort. The Xilinx reference design will serve as a baseline framework for ongoing 4.5G/5G wireless network research and the All Programmable Zynq SoC’s hardware, software, and I/O programmability give researchers the ability to quickly grow, develop, and evolve the NGFI design from the baseline as envisioned by CMRI.

 

For more in-depth information on C-RANs, see “Free one hour video tutorial on CloudRANs (CRANs) and Fronthauling. Watch now!” by Raghu Rao, Xilinx Principal Architect of Wireless Communications.

 

 

 

Recent Xcell Daily 5G blogs:

 

 

 

 

 

 

 

 

Enclustra preparing a sub-$100 Zynq-based Kickstarter project

by Xilinx Employee ‎06-29-2015 01:20 PM - edited ‎06-29-2015 01:23 PM (887 Views)

Enclustra is telegraphing its intent to bring a sub-$100 Zynq SoC module to market via Kickstarter. Want more info? (I do.) Go subscribe to the company’s newsletter to hear about the announcement when they kick off the Kickstarter campaign.

 

 

Enclustra Kickstarter Tease Image.jpg

Now through the end of August, you can get one Acromag XMC-7A200 conduction-cooled FPGA module based on a Xilinx Artix-7 A200T FPGA, an APCe8675 PCIe carrier card, and the XMC-7KA-EDK engineering design kit for the bundled price of $2995. Essentially, that’s like getting the $370 design kit for free. (For more information on the XMC-7A200 FPGA module, see “Acromag’s XMC-7A200 mezzanine module brings Artix-7 FPGA processing power to XMC developers.”)

 

Click here for a PDF of the offer.

 

 

 

Acromag XMC-7A200 Bundle.jpg

 

By Adam Taylor

 

So far on this journey, we have significantly increased performance by accelerating matrix multiplication using the Zynq SoC’s PL (programmable logic). However if you look at the code within the mmult() function, you will notice that not only is the function implemented in C++ but it also contains a number of pragmas. A pragma is a directive that tells the compiler—or SDSoC in this case—how it should process its input. Exploring these pragmas and their role in increasing performance provides a great starting point for looking at HLS (high-level synthesis) and how it is used within SDSoC and Vivado HLS.

Read more...

The 16Gbps GTH and 30.5Gbps GTY SerDes ports in Xilinx Virtex UltraScale and Kintex UltraScale devices incorporate bang-bang phase detectors for clock and data recovery (CDR). Some communications protocols including PONs (passive optical networks) need faster-than-CDR symbol-lock times. They need burst-mode CDR (BCDR). A new application note, XAPP1252 Burst-Mode Clock Data Recovery with GTH and GTY Transceivers, gives you all the information you need plus step-by-step instructions and a link to reference design files that augment the on-chip CDR with a BCDR Quick-Lock circuit for quicker, bounded lock times with UltraScale GTH and GTY transceivers.

 

 

BCDR Circuit.jpg

Take your pick from six live, online training classes being offered this summer by North Pole Engineering. (Actually they’re only as far north as Minnesota, but still….)

 

Here’s North Pole Engineering’s summer online class lineup:

 

 

Class

Registration Cutoff

Start Date

Essentials of FPGA Design

6/29/2015

7/2/2015

Vivado Design Suite Advanced XDC and STA

7/7/2015

7/14/2015

Designing with the UltraScale Architecture

7/13/2015

7/20/2015

VHDL and Advanced VHDL, Condensed

7/22/2015

7/29/2015

Essentials of FPGA Design

8/17/2015

8/24/2015

Zynq SoC Training for Experienced FPGA Designers

8/19/2015

8/26/2015

 

 

These are live, fully interactive classes with 2-way video and audio and a low student/instructor ratio for more effective class interaction. There’s also post-training support via email.

 

For more detailed info or to register, click here or call North Pole Engineering at (612) 305-0440 x225.

 

Note: North Pole Engineering is a Xilinx authorized training provider.

 

Two of the many reasons I watch Dave Jones’ EEVBlog videos is because they’re entertaining and because Dave frequently uncovers old uses of long-lost Xilinx FPGAs. This week’s “Mailbag Monday” video is another case in point. EEVBlog’s Mailbag Monday consists of nothing more than Dave opening his mail. People send him interesting bits of current and old electronics. This week in the mail, Dave received a Fluke One Touch 10/100 Network Assistant and about 16 minutes into his video, when he’s opened the Fluke analyzer for a mini teardown, Dave finds not one but two Xilinx XC3164A FPGAs with 1996 date codes — that’s nearly 20 years ago (!) —marshalling a 20MHz Analog Devices DSP/single-chip microcontroller.

 

Here’s a photo of the Fluke’s processor board from Dave’s video:

 

 

Fluke One touch 10-100 Network Assistant pcb.jpg

 

 

The above photo was captured at 15:55 in Dave Jone’s Mailbag Monday video.

 

 

 

Xilinx programmable devices have a long, successful history in the instrumentation and Test & Measurement worlds and the two XC3164A FPGAs in this Fluke network analyzer constitute just one example. The Xilinx XC3164 FPGAs each have 224 CLBs in a 16x14 array. According to the “Big Board” here at Xilinx HQ, the XC3164A FPGA was introduced in 1994 and was fabricated using 0.65 µm process technology. It’s now long obsolete.

 

These days, you’d implement the entire board, DSP and all, with just one Xilinx All Programmable device—possibly a Zynq SoC in this case. The smallest device in the Zynq SoC family, the Zynq Z-7010, has 28K logic cells, 80 DSP slices, and two 866MHz ARM Cortex-A9 MPCore processors with ARM NEON SIMD and double-precision floating-point extensions, and a couple of Gigabit Ethernet ports, all of which can easily cover the functional capabilities required by the old Fluke network analyzer in Dave’s quick teardown (or even a new 10/100/1000 analyzer designed today).

 

Here’s Dave’s video, in case you’re interested:

 

 

 

 

 

There’s a pyramid on the dwarf planet Ceres in the asteroid belt between Mars and Jupiter. The pyramid is three miles tall. How do we know this? The Dawn spacecraft now in orbit around Ceres sent photos:

 

 

Pyramid on Ceres.jpg

 

 

Image credit: NASA/JPL-Caltech/UCLA/MPS/DLR/IDA

 

 

The photo was captured by the Dawn spacecraft’s Framing Camera, a multi-talented refractive telescope with a 1024x1024-pixel CCD imager capped with an electronic shutter. Each of the spacecraft’s two framing cameras is controlled by its own FPGA-based DPU (data processing unit) developed at IDA (the Institut für Datentechnik und Kommunikationsnetze at TU Braunschweig) in Germany. The FPGA is a radiation-tolerant 90nm Xilinx Virtex-4QV. (For more information, see “Visit to a small planet: NASA’s Dawn spacecraft sends video postcard from Ceres in the asteroid belt.”)

 

 

 

If you’ve been waiting for a price drop on the Adapteva Parallella parallel-processing board (with a free Zynq SoC included in every purchase!), then today’s your day. If you haven’t heard of the Adapteva Parallela board, go read this blog post: “Adapteva’s Zynq-based parallel supercomputer: an update.” We’ll all wait for you here while you catch up.

 

Done?

 

Want to know how to get this deal of the day? It’s on Amazon. Click here. (Looks like this deal is US-only, to whittle down overstock.)

 

It’s not clear how long Crazy Andreas Olofsson will be in this generous mood, so you might want to act now.

 

Adapteva Parallela Board.jpg 

CESNET and INVEA-TECH develop FPGA-based bifurcated PCIe Gen3 x16 interface for 100G Ethernet designs

by Xilinx Employee ‎06-23-2015 09:52 AM - edited ‎06-23-2015 09:57 AM (1,643 Views)

100G Ethernet is not a problem any more.jpg

Line-rate forwarding of 100Gbps Ethernet traffic has been a huge challenge—if not impossible—for general-purpose CPUs. However, the major obstacle in the system is not CPU power (modern multicore CPU performance is gigantic); the problem lies in the PCI Express interface itself. The fastest PCIe Gen3 variant with 16 full-duplex lines, each running at 8 G transfers/sec in each direction, is a bidirectional 128Gbps. However, due to 128/130 bit encoding and other protocol overhead, the actual realized throughput drops to something like 100Gbps. Still good enough for full-duplex 100G Ethernet operation. However, there’s currently no FPGA in production that supports a PCIe Gen3 x16 interface. That’s a problem for 100G Ethernet designs, and yes there is now a solution to that problem.

 

 

CESNET and INVEA-TECH have developed an FPGA-based, full-duplex PCIe Gen3 x16 interface (two bifurcated PCIe Gen3 x8 interfaces) for 100G full-duplex Ethernet designs using a Virtex-7 H580T 3D FPGA and appropriate IP instantiated in the FPGA. (Note: You can read about a similar half-duplex design in “Need to get 100G Ethernet data stream into a host Intel CPU? PCIe bifurcation is the answer.”) Here’s a block diagram of the system:

 

 

 

CESNET and INVEA-TECH PCIe Gen3 x16 bifurcated interface.jpg

 

 

 

This full-duplex PCIe Gen3 x16 bifurcated interface didn’t just fall out of a box of standard IP. The final, successful design required some tweaking and optimization. The length and ordering of PCI Express transactions were fine-tuned by hand using a PCIe protocol analyzer to achieve optimal performance with Intel Xeon CPUs. Additional PCIe transaction buffers to extend standard Xilinx PCIe core capacity and compensate for long-latency PCIe reads were added as was extra transaction-tag space. Eight independent ring buffers for RX and eight for TX were allocated in RAM to allow multiple Xeon CPU cores to work independently in parallel without the need for inter-core communications.

 

For more information on this high-speed PCIe Gen3 x16 bifurcated interface, visit the INVEA-TECH Web page or contact INVEA-TECH directly at info@invea.com.

 

 

 

 

 

 

 

 

 

 

By Adam Taylor

 

Having now demonstrated that we can achieve excellent performance improvements with the Xilinx SDSoC development environment with just the simple click of a mouse, I would like to look a little deeper into how SDSoC performs this trick.

SDSoC accelerates functions within the PL (programmable logic) side of the Zynq SoC using something called the “connectivity framework,” which describes the logical and physical connections between the PL and PS (processor system) sides of the device. Unsurprisingly, SDSoC includes an API to allow transfers using this framework.

 

 

Read more...

Early this year, Xcell Daily visited Teraspeed Consulting’s booth at DesignCon where there was a demo setup of a 28Gbps backplane for testing. (See “28Gbps backplane demo highlights Samtec low-loss connectors using Virtex UltraScale FPGAs.”) The setup consisted of two intercommunicating Xilinx VCU109 Eval boards (based on 20nm Xilinx Virtex UltraScale VU095 FPGAs) plugged into high-speed, 20-inch backplane (24-inch total path length) through high-speed Samtec ExaMAX connectors. Teraspeed selected the Xilinx UltraScale VU090 FPGA to build the fastest possible demonstration vehicle for the Samtec ExaMAX connectors because of its clean 28Gbps SerDes transmitters and bullet-proof 28Gbps SerDes receivers. (Note: Samtec recently acquired Teraspeed Consulting.)

 

Teraspeed’s Scott McMorrow has just published two videos with an hour of material covering this setup and the lessons learned about the design, the materials, and the connectors needed to construct reliable backplanes that can operate above 25Gbps at the lowest possible cost. Well worth watching:

 

 

 

 

 

 

 

 

 

 

 

By Adam Taylor

 

 

So far in our journey with the Xilinx SDSoC development environment, we have created our first application, run it successfully on the ZedBoard, and obtained performance data for the multiply-and-add function when we run both the reference code and the code to be moved into the hardware within the PS side of the device.

 

Having established that both functions take a similar amount of time to execute, we are going to now move the multiply-and-add function into the PL (programmable logic) side of the Zynq SoC. It’s amazing how simple this is to achieve.

Read more...

The latest Xcell Journal cartoon caption contest ends on July 1 at 5 PM Pacific Time. There’s a Zynq-based ZYBO development board from Digilent as a prize for the best caption, as decided by a distinguished panel of judges.

 

Where will you find the cartoon in need of a caption? On page 68 of Xcell Journal, issue 91, where you will also find a pointer the long list of legally required disclaimers for such a contest.

 

Send your caption by email to xcell@xilinx.com. Include your name, job title, company affiliation (if applicable), a statement acknowledging that "I have read and agree to the full official rules located at www.xilinx.com/xcellcontest," and your mailing address in the body of the email.

 

No other methods of entry will be accepted.

 

Tempus fugit.

 

 

 

 

Photonfocus Hyperspectral Camera.jpg

 

The just-announced hyperspectral Photonfocus MV1-D2048x1088-HS02-96-G2 GigE video camera produces a 42-frames/sec video stream based on 25 spectral pass bands from 600nm to 975nm (from orange/yellow through near infrared), resulting in a 10-bit grayscale video representation. This hyperspectral GigE video camera is based on an IMEC snapshot mosaic CMV2K-SSM5x5-NIR sensor, which in turn is based on the CMOSIS CMV2000 2048x1088-pixel CMOS HD image sensor.

 

 

Read more...

Xilinx Authorized Training Provider and Alliance Program member Bottom Line Technologies (BLT) is teaching a course called “Xilinx for Managers.” The June 24 class is already sold out. Seats for the July 14 class in Columbia, MD appear to be selling out quickly.

 

Why are others going to this class? Here’s a list of skills to be gained:

 

 

  • 5 Essential elements of effective FPGA/SoC design - BLT's PSSST approach
  • Employ a disciplined methodology to manage FPGA/SoC-based designs
  • Architect, specify, and plan FPGA/SoC-based projects
  • Understand how Xilinx tools are employed
  • Understand the various Xilinx FPGA and SoC families, their overall functionality and capabilities
  • Assess an engineering candidate's ability to effectively design with FPGA/SoCs
  • Develop design teams to implement Xilinx FPGA/SoCs most effectively
  • Estimate Chip size and cost as early as practical
  • Appreciate common FPGA/SoC design challenges and know how to best address them
  • Recognize and mitigate risk factors to a project's schedule and cost
  • Cut through seemingly complex problems to stay on track
  • Get help when your internal resources are struggling

 

 

This one-day class is for managers, not design engineers. Labs are interactive walkthroughs so your brain won’t melt and leak out through your ear. Post-class coaching is also available.

 

Register here.

 

Note: BLT teaches other classes specifically for engineers.

 

 

A research group at Yonsei University working on future wireless communications systems has demonstrated a real-time, full-duplex LTE radio system at IEEE Globecom in Austin, Texas last December. The team is using a novel antenna approach and has been working with National Instruments SDR platforms and the LabVIEW graphical programming environment. The full-duplex prototype is based on the LTE downlink standard with the following system specifications:

 

  • Transmission bandwidth of 20 MHz
  • 72 MHz sampling rate
  • 15 kHz subcarrier spacing
  • 2048 fast Fourier transform (FFT) size
  • Variable 4/16/64 quadrature amplitude modulation (QAM)

 

Here’s a block diagram of the prototype system:

 

 

Full-Duplex LTE SDR Prototype Block diagram.jpg 

 

 

Note that the red rectangle in the block diagram performs the real-time baseband signal processing and digital self-interference cancellation required for full-duplex operaiton, implemented with a National Instruments PXIe-7965R FlexRIO FPGA module based on a Xilinx Virtex-5 SX95T FPGA. For further technical details, see “Prototyping Real-Time Full Duplex Radios” on the National Instruments Web site. Also, here’s a short 4-minute video about the project:

 

 

 

 

 

If you want to succeed in developing complex FPGA-based system designs, you need expertise in the use of timing constraints and static timing analysis. If you have these topics mastered, good for you! If not, here’s a chance to hone your skills to razor sharpness, for free in the relatively painless environment of your desk PC or laptop, courtesy of Doulos.

 

The Webinar—titled Quick Start Webinar on timing constraints and Xilinx Vivado—will discuss using FPGA-centric Xilinx Design Constraints (XDC), which are based on the ASIC-centric Systopsys Design Constraints (SDC). The Webinar takes place on Thursday, June 25.

 

That’s only ten days from today.

 

There are two Doulos Webinar sessions: one convenient for the UK, Europe, and Asia and the other for North America (and late afternoon in Europe). You can register for either one.

 

 

Here’s the Webinar agenda:

 

  • How timing constraints are used in the Vivado Design Suite
  • Timing paths; launch and capture edges; source and destination clocks;
  • Setup and hold requirements
  • Anatomy of a timing report; setup and hold checks; slack calculation
  • Generated clocks; auto-derived clocks
  • Setting input and output delays; minimum and maximum delays
  • Timing reports for inputs and outputs
  • Timing Closure Methodology: Baselining

 

Register here, now.

 

 

 

By Adam Taylor

 

 

Having looked introduced SDSoC in the last column, it’s now time to start working on how we get SDSoC up and running with a first example. We are going to be using the ZedBoard for this. As always, we will go more or less step by step with description as we do.

 

 

Image1.jpg

Read more...

Earlier this month, Xcell Daily covered the Cortus development platform for the company’s APS23 and APS25 32-bit RISC microcontroller cores. (See “Dev board based on Spartan-6 FPGA provides platform for SoC design, development based on Cortus 32-bit cores.”) The board is based on a Xilinx Spartan-6 LX75 FPGA, which is large enough to hold a processor core or two and more logic if you’re designing a small SoC. This is a truly low-cost FPGA prototyping platform for small SoC development and I saw one in operation at this week’s DAC 2015 conference in San Francisco. Below is a video of the board running.

 

How do we know it’s running? Watch the row of green LEDs in the upper left corner.

 

 

 

UltraScale VU440 3D FPGA with 4.4M logic cells spotted in the wild at DAC in San Francisco this week!

by Xilinx Employee ‎06-12-2015 03:33 PM - edited ‎06-18-2015 10:38 AM (1,311 Views)

I visited DAC this week in San Francisco looking particularly for the FPGA prototyping boards I’ve covered in the Xcell Daily blog. Found one! Here’s the S2C VU Prodigy Logic Module based on a 20nm Xilinx Virtex UltraScale VU440 FPGA, which brings 4.433M logic cells, 2880 DSP48E2 slices, and 88.6Mbits of Block RAM to the party in one device.

 

 

S2C Single VU440 Prodigy Logic Module at DAC.jpg 

 

S2C VU Prodigy Logic Module based on a Xilinx Virtex UltraScale VU440 FPGA

 

 

 

You’ll find a DDR4 SODIMM socket for memory expansion on the back of the board:

 

 

S2C VU440 Prodigy Logic Module DDR4 SODIMM socket.jpg

 

 

The Xilinx Virtex UltraScale VU440 3D FPGA is constructed using next-generation “Xinterposer” 3D IC technology jointly developed by Xilinx and TSMC. Use of 3D technology permits construction of a composite 3D FPGA with approximately 19 billion transistors that’s larger than the optical lithography tool’s reticle size allows.

 

You can get more information about this technology in the article “Next-generation 3D FPGAs” by Xin Wu, Woon-Seong Kwon, Suresh Ramalingam, which was just published in ChipScale Review Magazine.

 

There’s more information about the S2C Single VU440 Prodigy Logic Module in the Xcell Daily blog post “Phenomenal Cosmic Prototyping Power, Itty Bitty Package: The new S2C Single VU440 Prodigy Logic Module.”

 

 

The Fairchild Patent Notebooks: A dinner presentation with Computer History Museum’s David Laws

by Xilinx Employee ‎06-12-2015 02:45 PM - edited ‎06-12-2015 04:45 PM (1,038 Views)

David Laws 1.jpg

 

Last night was the annual IEEE-CNSV (Consultants Network of Silicon Valley) Dinner and the guest speaker was David Laws, who currently serves as the Semiconductor Curator at the Computer History Museum in Mountain View. Laws spoke about an incredible artifact collection—perhaps the semiconductor industry’s single most important collection by far: The Fairchild Patent Notebooks. Among the many innovations documented in these 1334 hand-written notebooks are Jean Hoerni’s invention of the planar process and Robert Noyce’s extension of that process to connect multiple components on one silicon die to create the modern monolithic integrated circuit. These notebooks speak for the people who launched Silicon Valley, in their own words.

 

Laws is a semiconductor industry veteran having worked for Fairchild, Litronix, AMD, and others so he has a deep-set feel and an apparent fondness for the subject. The Fairchild patent notebooks made their way to the museum in a most circuitous way. They came from Texas Instruments, which purchased National Semiconductor in 2011. National took possession of the notebooks when it acquired Fairchild in 1987.

 

Of the many notebook pages Laws projected during his dinner speech, I particularly noted three for this blog:

 

December 1, 1957: Jean Hoerni documents his ideas for silicon wafer oxide insulation and masking—the fundamental semiconductor planar process. He got the idea in the shower one morning. But Hoerni didn’t use silicon-dioxide insulation to create ICs at first—that would take another three years to realize. He did it to save Fairchild from oblivion.

 

By 1959, Fairchild had $8 million in contracts for high-reliability, double-diffused mesa transistors, many of which were destined to go into Minuteman missile guidance computers. There was a problem however. One in 10,000 transistors would short out if tapped lightly. Tapping dislodged a sliver of metal inside of the transistor can and the metal would unfortunately short a junction in the unpassivated transistor—bye, bye transistor. Hoerni’s oxide insulation made the mesa transistor impervious to such faults.

 

 

Jean Hoerni Notebook page from 12-1-57.jpg

 

 

Page from Jean Hoerni’s Patent Notebook documenting the planar process. December 1, 1957.

Witnessed by Robert Noyce

 

 

 

January 23, 1959: Robert Noyce invents the metal interconnect layer needed to connect multiple devices on the same silicon die. This is the breakthrough needed to make monolithic integrated circuits.

 

 

Robert Noyce Notebook page from 1-23-59.jpg

 

 

Page from Robert Noyce’s Patent Notebook extending Hoerni’s planar process to an IC—a simple full-adder logic circuit built from a diode matrix. January 23, 1959.

 

 

October 8, 1962: PhD physicist Frank Wanlass documents the basic CMOS structure that now dominates the semiconductor industry. He stumbles onto an unusual behavior of the device but does not pursue it. It later turns out to be oxide tunneling and charge storage, the basic phenomena underlying EPROM storage.

 

The ideas and innovations in these notebooks, in conjunction with the patents developed from this work, constitute the archaeological history of the semiconductor industry. Patents have become extremely important in the semiconductor industry. Last year, when Xilinx celebrated its 30th anniversary, the press release mentioned the company’s 3500+ patents and 60 industry firsts in addition to celebrating the company’s three decades in business.

 

 

 

The Computer History Museum has an active campaign to raise the funds needed to restore and conserve these 1334 Fairchild patent notebooks. Here’s a video about that campaign:

 

 

 

 

 

 

 

Acromag’s XMC-7A200 mezzanine module brings Artix-7 FPGA processing power to XMC developers

by Xilinx Employee ‎06-11-2015 03:46 PM - edited ‎06-11-2015 04:04 PM (1,055 Views)

Acromag XMC-7A200 Artix-7 FPGA Module Photo.jpg

 

 

The Acromag XMC-7A200 User-Configurable Artix-7 FPGA Module with Plug-In I/O brings the processing power of the largest Xilinx Artix-7 FPGA to the XMC form factor including 215,360 logic cells, 740 DSP48 slices, and 13.14Mbits of Block RAM. The board also includes 1Gbyte of x64-bit (4x16-bit) DDR3 SDRAM and 512Mbits of parallel Flash memory with ample room to store a large program for a Xilinx MicroBlaze 32-bit RISC processor instantiated in the FPGA. The board also sports P15 and P16 XMC connectors and a P4 PMC rear-I/O connector for high-speed expansion.

 

 

Here’s a block diagram of the board.

 

 

Acromag XMC-7A200 Artix-7 FPGA Module.jpg

Leading Lights Award 2015.jpgLight Reading, a leading online publication for the network and communications industry, has just presented Xilinx with a 2015 Leading Lights award for Outstanding Components Vendor at an awards dinner held in Chicago on June 8 in conjunction with this week’s Big Telecom Event.

 

There’s a very big reason that explains why Xilinx won this award.

 

Equipped with the right IP and software, Xilinx All Programmable FPGAs and SoCs can implement single-chip systems, replacing ASSPs and ASICs entirely. This capability is critical in leading-edge applications where shipping volumes have not yet become—and may never become—sufficiently large to attract the ASSP vendors or to justify the NRE associated with cutting-edge, nanometer ASIC development.

 

This is precisely the current situation for networking products that implement 100G and 400G Ethernet and other equally high-speed networking protocols including OTN.

 

Quite simply, there is no better way to implement these products—especially with the introduction of the latest Xilinx 20nm UltraScale and 16nm UltraScale+ devices.

 

The impact of the Xilinx All Programmable device portfolio on the development of Smarter Networks based on next-generation networking and communications systems is most visible in emerging applications including SDN and NFV, data-center compute acceleration, storage, and high-speed wired communications including Nx100G Ethernet and >400G OTN, 4G and pre-5G wireless radios, and wireless backhaul. Xilinx’s innovation in this space is apparent: Xilinx is the only company delivering a single-chip solution for 500G OTN transponders and 2x100G OTN switching applications with fully validated reference designs.

 

Further, Xilinx, Huawei, and Spirent have demonstrated a prototype 400G Ethernet core router, based on Xilinx's high-end FPGAs. (See “Huawei and Xilinx unveil prototype 400GE Core Router at OFC 2104. FPGAs do the heavy lifting.”) This is the first prototype system to validate 400G Ethernet technology, which is still in its pre-standards phase. When standards are in flux, as they are here, Xilinx All Programmable devices are especially useful in getting early products to market. In addition, JDSU and IXIA have announced 400G Ethernet test systems based on Xilinx technology. (See “JDSU 400G Ethernet test platform at OFC 2015 based on Xilinx 20nm UltraScale devices”, “Single-chip 100G and 400G demos at next week’s OFC 2015 highlight UltraScale FPGA and Xilinx IP networking capabilities”, and “Xilinx and Ixia present 400GE and 25GE testing solutions at OFC 2015” for more information.)

 

Xilinx owns 100% of the 400G Ethernet platforms announced to date.

 

The Leading Lights awards are the telecom industry's most prestigious awards program and focus on next-generation communications technologies, applications, services, and strategies. Xilinx won the 2015 Leading Lights award for Outstanding Components Vendor out of a field of seven finalists in the category.

 

For more detailed information on Xilinx and Smarter Networks, see “A Generation Ahead: SMARTER NETWORKS.”

 

 

 

100G Ethernet NIC from Hitech Global – A PCIe card powered by a Xilinx Virtex-7 H580T FPGA

by Xilinx Employee ‎06-10-2015 01:59 PM - edited ‎06-10-2015 02:04 PM (900 Views)

Hitech Global has announced the HTG-728 100G NIC (network interface card) PCIe Gen3 board based on the Xilinx Virtex-7 H580T FPGA. On board, there’s a CFP2 (4x25Gbps) and a CFP4 (4x25G) card cage for optical Ethernet modules. In addition, for board-to-board and other in-box system interconnect, there are two Avago MiniPOD optical receiver/transmitters, each with twelve TX and RX lanes for an aggregate bandwidth of 120Gbps in addition to the board’s x16 PCIe Gen3 interface.

 

 

Hitech Global HTG-728 100G NIC.jpg

 

Hitech Global HTG-728 100G NIC PCIe Gen3 board

 

 

 

Here’s a block diagram of the board:

 

 

Hitech Global HTG-728 100G NIC block diagram.jpg

 

 

Hitech Global HTG-728 100G NIC Block Diagram

 

 

Clearly, the board is extracting a lot of benefit from the Virtex-7 H580T FPGA’s eight 28.05Gbps GTZ and forty-eight 13.1Gbps GHT SerDes ports.

 

CAPI Acceleration Development Kit brings coherent FPGA acceleration to IBM POWER8 servers

by Xilinx Employee ‎06-10-2015 01:04 PM - edited ‎06-10-2015 01:29 PM (1,232 Views)

Alpha Data has announced a CAPI Acceleration Development Kit based on its ADM-PCIE-7V3 PCIe board incorporating a Xilinx Virtex-7 690T FPGA, IBM’s CAPI (Coherent Accelerator Processor Interface) protocol, a library of Alpha Data CAPI reference designs, and IP from Xilinx and 3rd-party vendors. CAPI is IBM’s high-speed acceleration protocol for servers based on the company’s POWER8 superscalar, symmetric multiprocessors used in its high-end servers. The protocol connects custom acceleration engines to the coherent fabric of the POWER8 chip that removes both the overhead of an I/O subsystem and the software required to communicate through such a subsystem, which produces accelerators with much better performance.

 

 

Alpha Data ADM-PCIE-7V3.jpg

 

Alpha Data ADM-PCIE-7V3 PCIe accelerator board based on a Xilinx Virtex-7 FPGA

 

 

 

CAPI as implemented on IBM’s POWER8 systems provides a high-performance way to implement client-specific, computation-heavy algorithms on an FPGA. These accelerated algorithms can replace application programs running on a POWER8 processor core. Using CAPI, POWER8 systems can treat the FPGA-based accelerator as a coherent peer to the POWER8 processors. Because of CAPI's peer-to-peer coherent relationship with the POWER8 processors, data intensive programs are easily offloaded to the FPGA and these offloaded functions operate as part of the application, which results in higher system performance with a much smaller programming investment. In IBM’s view, this approach allows hybrid computing to be successful across a much broader range of applications.

 

Here’s a block diagram of the way this all works:

 

 

CAPI Block Diagram.jpg

 

Alpha Data CAPI Acceleration Development Kit Hardware Block Diagram

 

 

 

The Alpha Data CAPI Acceleration Development Kit includes the PSL (Power Service Layer), which resides on the FPGA and provides the infrastructure connection to the POWER8 chip; examples of user-defined AFUs (Accelerator Function Units); as well as CAPI-specific OS Kernel extensions and library functions. This kits includes all needed components to significantly reduce development time.

 

Note: This announcement is part of the OpenPOWER Summit taking place today in Beijing.

 

 

 

 

 

 

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About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.