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MathWorks Logo.jpgMathWorks has just announced that its MATLAB and Simulink embedded, model-based design tools now automatically generate optimized code for ARM Cortex-A processors including the dual ARM Cortex-A9 MPCore processor in all Xilinx Zynq SoCs. In this case, “optimized” means faster execution time, reduced memory usage, and code acceleration through the use of the NE10 DSP support library for the 128-bit ARM NEON SIMD Engine. In addition, MathWorks’ Simulink offers built-in target support for the Xilinx Zynq SoC.

 

 

PRO DESIGN’s new proFPGA Zynq 7000 module provides a fast way to prototype ARM-based SoCs and related IP. The $8600 board comes loaded with a Xilinx Zynq XC7Z045 or XC7Z100 All Programmable SoC, which combines two ARM Cortex-A9 MPCore processors with a large amount of Xilinx Kintex-7 FPGA fabric. The on-chip Processor System also includes several interfaces including USB 2.0 OTG, Gigabit Ethernet, and an ARM JTAG debug interface. This new board is part of a growing proFPGA product family specifically designed for SoC, ASIC, and IP Prototyping and pre-silicon software development.

 

 

proFPGA Zynq 7000 module.jpg

Adrian Cosoroaba and Terry Magee gave a detailed presentation on the DDR4 SDRAM interface designed into the new Xilinx UltraScale All Programmable FPGAs at MemCon earlier this month. This interface is designed to take DDR SDRAM to 2400Mbps and beyond while lowering the interface power consumption. To do this, the Xilinx engineers had to turn the DDR4 interface problem on its head. Instead of designing DDR4 capability into the UltraScale I/O PHYs, they designed a DDR4 I/O PHY from the ground up and then expanded its abilities to support other I/O requirements. The result: a basic 13-bit programmable byte lane that’s first and foremost a DDR4 PHY.

 

If you’re coming from the SoC world, it might not be obvious why Xilinx has taken this approach. It’s because I/O pins are a scarce resource. While there are hundreds of thousands or millions of logic cells and flip-flops, multiple Mbits of block RAM, and thousands of DSP slices, there are only a few hundred I/O pins due to physical package limitations. Thus the I/O pins must be programmable and flexible enough to cover any possible I/O use ranging from driving banks of DDR4-2400 SDRAM to blinking an LED and pretty much everything in between. For UltraScale architecture FPGAs, it made sense to do the hard portion of the I/O design first—the DDR4 PHY—and then add in the easier stuff.

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NBASE-T Logo.jpgPushing 1Gbps Ethernet cable to 2.5 or 5Gbps promises to propel data center bandwidth efficiency and throughput to new heights at very low cost. That’s precisely the intent of the new NBASE-T Alliance, just announced by founding members Cisco, Aquantia, Freescale, and Xilinx. The idea is to develop standards that allow 2.5G and 5G Ethernet operation over conventional Cat 5e and Cat 6 cabling currently used everywhere for 1G Ethernet connections.

 

As the alliance Web site says, Cat 5e and Cat 6 cables currently “represent close to 100 percent of the installed cable infrastructure in enterprises around the world.”

 

NBASE-T technology increases network speeds over existing Cat 5e/Cat 6 cables up to 5 Gbps at lengths to 100m using advanced (yet easy to use) physical layer integrated circuit technology. Because it’s copper-based, NBASE-T also supports all PoE (Power over Ethernet) standards—unlike fiber-based connections.

 

The NBASE-T Alliance lists the following target applications for this technology:

 

  • Wireless LAN (WLAN), connecting the newest generation of 802.11ac WiFi Access Points (APs) to Ethernet switches in wiring closets (indoor and outdoor deployments)
  • Small cells
  • Enterprise wired infrastructure, with client/desktop PCs connected to Ethernet switches
  • Security camera
  • Digital signage
  • Industrial/compact switches

 

For additional information about the PHY technology behind NBASE-T, see “Boost data center bandwidth by 5x over Cat 5e and 6 cabling. Ask your doctor if Aquantia’s AQrate is right for you.”

The future of semiconductor memory will be rich in choices for system designers. If you’re looking for some clarification of those options, download a free copy of “The Rise of Serial Memory and the Future of DDR,” a new Xilinx White Paper (WP456) written by Tamara Schmitz and released just this week. The White Paper discusses the memory market trends, with DDR3 the clear market leader at the moment, and then discusses possible successors to DDR3 including:

 

  • Hybrid Memory Cube (HMC)
  • MoSys Bandwidth Engine 2 (BE2)
  • High Bandwidth Memory (HBM)
  • Ternary Content Addressable Memory (TCAM)

 

(Note: Xilinx UltraScale devices can control all of these memory types.)

 

 

 Market Trends for DRAM Memory 2014.jpg

Next week at Vision Stuttgart 2014, you’ll be able to see some real-world demonstrations of the Xilinx Zynq SoC used for Smarter Vision applications including pattern matching, bar-code reading, and real-time OCR (optical character recognition). The OCR demo is based on MVTec’s HALCON Machine Vision Software running on the recently introduced, Zynq-based Avnet Smart Vision Dev Kit.

 

 

Avnet Smart Vision Dev Kit based on PicoZed SOM.jpg

 

Avnet Smart Vision Development Kit

 

 

You’ll also be able to see a demo of Silicon software’s Visual Applets, which give you a graphical way to develop machine-vision apps very quickly.

 

For more information on the Avnet Smart Vision Dev Kit, see “Smart Vision Dev Kit pairs Zynq-based PicoZed SOM with Aptina-based 1.2Mpixel camera module.”

 

For more information about MVTec’s HALCON, see “End-to-End Smarter Vision Demo at SPS IPC Drives Conference Showcases VisualApplets, HALCON, and Zynq.”

 

For more information about Silicon Software’s Visual Applets GUI-based embedded vision development environment, see “Silicon Software, Xilinx to demo high-productivity Visual Applets vision-app builder at Embedded Vision Summit next week” and “How would you like to get a 10x speedup in your image-processing or optical-inspection system using the Zynq SoC?

 

ARM and AMD announced that they have joined RapidIO.org to work with existing members of the standards organization to develop an open specification for coherently connecting multiple 64-bit ARM processors. RapidIO is an open-standard, switched fabric interconnect with a large partner ecosystem. There’s now a dedicated ARM 64-bit Coherent Scale Out task group within RapidIO.org. The task group’s working members include AMD, ARM, Cavium, Freescale, IDT, IIT Madras, Mercury Systems, Mobiveil, Texas Instruments, and Xilinx.

 

RapidIO is currently the only standards-based interconnect with a defined coherent overlay, which makes a good foundation for a standards-based interconnect for closely coupled ARM 64-bit processors. The task group will be looking at optimal ways to map ARM’s Cache Coherent Interconnect to RapidIO. As a member of the task group, Xilinx is tracking these developments so that the company will be prepared to support the spec when it’s ready. Xilinx already offers RadipIO Gen 2 Endpoint IP and Serial RapidIO Gen 1.3 IP with extensions for Gen 2, 5Gbps line rates in its LogiCORE IP family.

 

By Adam Taylor

 

Having correctly installed the SDK on our virtual machine, we need to look at how we can create our own application using Linux. This often requires a new definition of the Zynq SoC’s hardware.

 

The first thing we need to do is ensure that we have downloaded and installed the Vivado Design Suite and SDK onto our virtual machine. We will need these applications to create the Zynq SoC hardware definition and to develop the software environment as well.

 

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Smart Vision Dev Kit pairs Zynq-based PicoZed SOM with Aptina-based 1.2Mpixel camera module

by Xilinx Employee ‎10-24-2014 09:57 AM - edited ‎10-24-2014 10:12 AM (883 Views)

Avnet has just introduced a Smart Vision Development Kit based on the company’s new PicoZed SOM (system on module), which incorporates the Xilinx Zynq Z7015 SoC. A device-locked license for the Xilinx Vivado Design Edition is included. The kit also includes a swappable camera module based on an Aptina imager and an I/O carrier card with connectors for the Aptina 1.2Mpixel camera module, HDMI, two Ethernet ports, and a pair of CoaXPress ports for transporting video and images over coaxial cables at rates to 6.25Gbps. In addition to CoaXPress, the kit supports machine-vision communication protocols including Ethernet-based GigEVision (GEV) and USB3Vision (U3V). There’s also an optional add on card for CameraLink.

 

 

 

Avnet Smart Vision Dev Kit based on PicoZed SOM.jpg

 

 

Avnet Zynq-based Smart Vision Development Kit

 

 

The kit also supports other camera modules based on other imaging sensors including ON Semiconductor’s new PYTHON image sensor family and Toshiba America Electronic Components’ TCM3232PB full HD (1080p high-definition) image sensor, newly designed for security and surveillance applications. The PYTHON sensor image family is ideal for high-end machine vision applications, and features a true pipelined and triggered global shutter. TAEC’s TCM3232PB delivers high-quality video capture at 60 frames per second, utilizing the Toshiba High Dynamic Range (HDR) technology for better real-time image quality.

 

Suggested applications for this kit include machine vision, video analytics, product inspection, robotics, QA, intelligent traffic monitoring, bar-code scanning, counterfeit currency detection, and sports simulation.

Intilop has just announced availability of its TCP Hardware Accelerator (a TCP Offload Engine or TOE)—which manages 16K concurrent TCP sessions—pre-ported and tested on an Alpha Data ADM-PCIE-7V3 card, which is based on a Xilinx Virtex-7 VX690T FPGA.

 

 

Alpha Data ADM-PCIE-7V3.jpg

 

 

Alpha Data ADM-PCIE-7V3 card, which is based on a Xilinx Virtex-7 FPGA

 

 

This offering provides ultra-low-latency (77 nsec) protocol acceleration at 10G line rates—orders of magnitude faster than software-based TCP implementations. Intilop is targeting this accelerator at data-center applications including Cloud Computing, Network Security, Telecomm, and server appliances in government and enterprise systems. Customers can add value through their own hardware IP using the “super simple” FIFO-based interface to the TCP Hardware Accelerator.

 

The $89 Xilinx Spartan-6 FPGA LX9 MicroBoard is another low-cost way to learn FPGAs

by Xilinx Employee ‎10-22-2014 11:41 AM - edited ‎10-22-2014 11:43 AM (960 Views)

 

Yesterday while Googling up some information for the blog about the miniSpartan6+ development board, I stumbled upon the $89 Xilinx Spartan-6 FPGA LX9 MicroBoard. I’m sure I haven’t written about this little FPGA development card, even though it’s been around for a while, so now’s the time. The Spartan-6 MicroBoard is a complete, low-cost way for you to get into FPGA development with Xilinx Spartan-6 FPGAs. It uses a USB port for both power and JTAG programming so all you need is a USB cable (included) and a host PC. Best of all, for someone like me, the board has a pre-loaded configuration so it can do something right out of the box. There’s also a series of video tutorials, Avnet Speedway Design Workshops, and an active Avnet support forum to go with this board.

 

 

Avnet Spartan-6 MicroBoard.jpg

 

 

Even though tiny, the Xilinx Spartan-6 FPGA LX9 MicroBoard includes:

 

  • Spartan-6 XC6SLX9-2CSG324C FPGA
  • 64Mbytes of LPDDR SDRAM
  • 128Mbits of Multi-I/O SPI Flash Memory
  • 10/100 Ethernet PHY
  • USB-to-UART port
  • On-board USB JTAG circuitry
  • Two Digilent Pmod compatible headers (2x6) for easy peripheral device expansion
  • Single-chip, 3-rail power with Power Good indicator
  • TI CDCE913 programmable VCXO clock synthesizer chip
  • Over-voltage and ESD protection on USB
  • Four programmable LEDs
  • 4-bit DIP switch
  • Reset and PROG push-buttons
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Napatech NT40E3-4-PTP and NT4E2-PTP.jpg

 

Dell OEM Solutions now offers 4G and 40G Napatech Acceleration Platforms based on Dell PowerEdge servers and Napatech PCIe accelerator cards. It is paired with the Dell PowerEdge R720 2S/2U rack server, which is based on Intel Xeon E5-2600 or E5-2600v2 processors. The Napatech NT40E3-4-PTP card used in the 40G Acceleration Platform is a 40Gbps accelerator with four 10Gbps SFP+ ports. It is paired with the Dell PowerEdge R620 2S/1U rack server, which is based on Intel Xeon E5-2600 processor. The Napatech NT4E2-4-PTP card used in the 4G Acceleration Platform is a 4Gbps accelerator with four 1Gbps SFP ports. Both Napatech accelerator boards used in the Dell Acceleration Platforms are based on Xilinx Virtex-7 FPGAs.

 

The boards provide full packet capture and analysis of Ethernet LAN data with zero packet loss for all frame sizes, providing intelligent features for flow identification, filtering, and distribution with extremely low CPU load. Flexible time synchronization support includes support for IEEE 1588-2008 (PTP v2).The accelerator boards are designed for in-line applications.

 

Dell OEM Solutions has helped customers in key vertical markets accelerate time to market through customizable Tier-1 OEM technologies for more than 15 years. The Napatech Acceleration Platforms are the latest products in the company’s line, designed for development of high-performance network management and security appliance products. These are pre-tested and pre-integrated products for the data center, so these platforms reduce the time needed to develop and deploy new products for that market.

 

 

 

For more information, download and read the White Paper titled “Dell and Napatech: Accelerating Appliances”.

 

 

For more information on how Napatech has developed these high-speed PCIe accelerator cards for data-center applications, see “FPGAs as business-model enablers: Napatech at the Ethernet Technology Summit.”

 

 

miniSpartan6+ Kickstarter FPGA dev board update + video of HDMI I/O and processing

by Xilinx Employee ‎10-21-2014 03:00 PM - edited ‎10-21-2014 08:30 PM (1,351 Views)

The latest update on Scarab Hardware’s miniSpartan6+ FPGA dev board, a funded Kickstarter project (11x over its funding goal), appears here. As you can see, they’re assembling boards:

 

 

miniSpartan6+ assembled boards.jpg

 

 

Shipping should commence this week. Meanwhile, there’s a video of the board being used to generate HDMI video and to input, process, and output HDMI video. The FPGA configuration for the HDMI processing and I/O is based on Mike Field’s FPGA work as posted on his Hamsterworks site.

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Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

by Xilinx Employee ‎10-20-2014 10:23 AM - edited ‎10-21-2014 12:44 PM (886 Views)

By Adam Taylor

 

As I discussed last week, Petalinux is the official Linux distribution for the Zynq SoC. To get the most out of this distribution, we need to be able to build our own version. This requires development on a Linux system. Now, not all of us develop on these systems so creating a new machine can be expensive and time consuming. I will therefore be using a Virtual Machine to provide access to the Petalinux distribution. I have used a similar approach previously to use the CERN libre Filter design tool and it has worked well for me.

 

I’ll be using the Oracle VM Virtual Box machine and creating an Ubuntu installation of Linux on this virtual machine. This is very simple to achieve. First, download the VM virtual box and an Ubuntu ISO onto the hard drive of your host machine.

 

Once you have installed the VM Virtual box the next step is to select new on the virtual box manager and create your virtual Linux machine.

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Best-in-class software development teams deliver embedded products with 0.1 bugs per thousand lines of code. They consistently beat the schedule without grueling overtime.

 

Does that sound like your team?

 

No? Then what actions are you taking to improve your team's results?

 

Hoping for things to get better won't change anything. Overly general platitudes like “trying harder” and “working smarter” never work.

 

What does work? Getting expert advice from people who have been there and done that.

 

My good friend Jack Ganssle is teaching his one-day seminar “How to Develop Better Firmware Faster” three times next month. Jack knows more ways to mess up software development than any three other people I know. Fortunately, he also knows how to deal with these problems and he’s been telling people how they can do the same for many years now.

 

If software bugs and other development nuisances are biting you, Jack’s one-day course will teach you practical—and proven—ways to develop better firmware faster.

 

What have you got to lose? A day of your time? The next major software bug will kill at least a week of your schedule. Best to call the exterminator now.

 

The three November classes will take place at:

 

Baltimore, MD – November 7, 2014

Santa Clara, CA – November 14, 2014

Germany (just outside of Stuttgart) – November 28th, 2014

 

Register here. Tell them Steve sent you.

COVE-2 CubeSat based on Space-Grade Virtex-5Q FPGA passes 6-month operations milestone

by Xilinx Employee ‎10-17-2014 01:13 PM - edited ‎10-17-2014 01:13 PM (1,105 Views)

 

By Patricia Steele, Xilinx Employee Communications

 

 

M-Cubed-COVE CubeSat.jpg

 

M-Cubed/COVE-2 CubeSat (Image Credit: University of Michigan)

 

 

In December 2013, University of Michigan - Ann Arbor in conjunction with Jet Propulsion Laboratories, California Institute of Technology, and NASA's Earth Science Technology office launched into space the M-Cubed/COVE-2 CubeSat (a mini satellite used for space-science research and technology verification). Onboard the CubeSat sits the Virtex-5QV (V5QV) FPGA. The Virtex-5QV is the first of its kind - combining rad-hard technology with re-configuration capability used for high-performance processing.

 

 

COVE Virtex-5Q Processor Board.jpg

 

 

The COVE FPGA processor board (Image Credit: NASA/JPL)

 

 

M-Cubed's mission was two-fold. The primary assignment was to validate the Technology Readiness Level (TRL) of the new, on-board hardware and software. Pending success, the secondary undertaking was to perform a Decadal Survey for Aerosol Science (describes the role of clouds and aerosols in climate changes that can affect global warming) for the Aerosol-Cloud-Ecosystem.

 

One of the new technologies was an algorithm designed for NASA's Multiangle Spectropolarimetric Imager (MSPI), a multi-directional, multi-wavelength, high-accuracy polarization camera that processes 95 Mbytes/second of raw video data. Additionally, the Virtex FPGA would reduce this data by two-orders of magnitude. With no loss of information and in real-time, data would then transmit back down to Earth.

 

After many months in orbit, M-Cubed's primary mission was a success. According to Dr. Charles Norton of JPL and Cal Tech, "We recently passed our 6-month minimum operations milestone and have already met all of the Level-1 flight requirements for the payload and the mission. [The] team has been tracking housekeeping data on the Xilinx V5QV, and the image-processing algorithm has performed flawlessly on the FPGA hardware throughout the flight experiment." With this success, Virtex has advanced the TRL for future space-based MSPI instruments. Thus, the secondary mission began. Today, the CubeSat continues to collect, process, and successfully send back massive amounts of compressed MSPI video and data to NASA.

 

Note: This story by Patricia Steele originally appeared on the internal Xilinx Crossroads employee site

Teardown Thursday: See the Zynq-based NI VirtualBench and Cloudium IMP torn apart live at ARM TechCon.

by Xilinx Employee ‎10-16-2014 04:33 PM - edited ‎10-16-2014 04:35 PM (969 Views)

Earlier this month at ARM TechCon, I had the pleasure of moderating a double teardown panel at ARM TechCon with Kyle Bryson, Principal Architect at National Instruments and John Hickey, CEO of Cloudium Systems. First, we tore apart the National Instruments VirtualBench, an All-in-One Benchtop Instrument that combines the functions of an MSO (mixed-signal oscilloscope), a logic analyzer, a digital multimeter, an arbitrary waveform generator, and a programmable power supply. There are also a few software-controlled digital I/O lines for creating test and control systems. Next, we tore apart a Cloudium Systems Integrated Media Platform, a small set-top-box-like, cloud-oriented server designed to handle multiple compressed video and audio streams.

 

Both of these products are based on the Xilinx Zynq SoC and the following video shows you how the two products were designed and constructed and what Zynq features were used to realize the designs.

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According to this Mathworks press release, the latest MATLAB Release 2014b adds direct Xilinx Vivado integration to the package’s HDL Coder and Vivado support for FPGA-in-the-loop verification to HDL Verifier.

 

New Zynq-based SDR Reference Design supports Public Safety and Military LTE Radio Development

by Xilinx Employee ‎10-14-2014 06:15 AM - edited ‎10-14-2014 06:20 AM (1,827 Views)

Avnet Zynq 7000 SDR Eval Kit.jpg

Xilinx and SAI Technology have announced the availability of the first LTE UE (User Equipment) Software Defined Radio (SDR) reference design based on the Xilinx Zynq All Programmable SoC. The reference design can be used to develop public safety radios capable of voice, image, and video communications and has been implemented using the Vivado HLS (High-Level Synthesis) tool to make it easy for SDR developers to customize all protocol layers using high-level programming-language descriptions. You can immediately start working with this reference design using the Zynq-7000 All Programmable SoC/AD9361 Software-Defined Radio Systems Development Kit available from Avnet.

Leigh and Branham Robotics teams at the STEM Encampment 2014.jpgSeveral hundred Bay Area Boy Scouts and Cub Scouts passed through the Xilinx booth at the San Francisco Bay Area Council STEM (Science, Technology, Engineering, and Mathematics) Encampment, a day-long event held at the Alameda County Fairgrounds in Pleasanton on Saturday, October 11. Xilinx participated in the STEM Encampment to help these young people and their parents learn about the company and some of its youth-oriented community support activities and about Xilinx products, the semiconductor industry, engineers and engineering. David Manley and Steve Leibson from Xilinx staffed half of the company’s double-wide booth and explained the world of Xilinx and engineering to an endless stream of young people ranging from preschool to High School age. Several student members of Xilinx-supported robot teams from Leigh and Branham High Schools in San Jose occupied the other half of the Xilinx STEM Encampment booth. They were the real stars of the event, getting the lion’s share of the attention in the Xilinx booth with their live robotic games and activities.

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Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

by Xilinx Employee on ‎10-13-2014 10:09 AM (1,570 Views)

 

By Adam Taylor

 

Having spent the last few blogs looking at operating systems and AMP (asymmetric multiprocessing), a natural progression is to look at running Linux on the MicroZed. We’ve not yet discussed running Linux on the Xilinx Zynq SoC. Linux has become a major embedded operating system so by discussing it now, we’ll also be discussing symmetric multiprocessing, killing two birds with one stone—so to speak.

Since its creation by Linus Torvalds—who wrote Linux as a personal project in 1991 while he was a computer science student at the University of Helsinki—Linux has become one of the world’s most widely adopted operating systems and has become increasingly popular as an embedded OS. With a large number of software developers now familiar with both the Linux kernel and application development for Linux, it stands to reason that we would wish to run Linux on the PS side of the Zynq SoC.

 

Linux is capable of running on one ARM Cortex-A9 MPCore processor core or on both of the cores in the Zynq SoC. When we run the OS on both cores, a single operating system is in control and this makes it an SMP (symmetric multiprocessing) system.

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Adrian Cosoroaba and Terry Magee from Xilinx are giving a talk titled “High Performance DDR4 interfaces with FPGA Flexibility” at 2:40pm on October 15—next week at Memcon at the Santa Clara Convention Center. Magee, a Principal Engineer at Xilinx, architected the DDR4-2400 PHY used in the new Xilinx UltraScale All Programmable FPGAs and the talk will discuss how the Xilinx PHY design team put together a reliable DDR4-2400 memory interface with the extreme flexibility (compared to an ASIC) and low power consumption required by programmable FPGA I/O pins.

 

The demanding DDR-2400 capabilities had to be added without compromising the I/O pin’s ability to perform other tasks as challenging as operating as a high-speed serial I/O port or as simple as an LED driver. In addition, the same high-speed PHY would be expected to drive DDR3-2133, DDR3L-1866, and LPDDR3 SDRAM; low-latency RLDRAM 3; and QDRII+ and QDR IV SRAM. That’s a tall order for one I/O pin yet it’s the sort of capability and flexibility that FPGA PHY designers are expected to create.

 

The solution to developing a DDR4-2400 PHY was to “turn the problem on its head,” to steal a line from one of the presentation slides. I’m not going to tell you how that was done—not just yet—because I’ll steal no thunder from next week’s presentation. I will tell you it’s not nearly as simple as purchasing a 3rd-party PHY IP block and dropping it into the design.

 

However, I will give you a graphical preview:

 

 

UltraScale DDR4-2400 PHY Eye.jpg

 

 

Interested? Register by clicking here. (It’s free.)

Do you need a clear understanding of the advantages and disadvantages of FPGAs, NPUs, and Multicore CPUs for packet processing? You will get one at the Linley Processor Conference 2014 in Santa Clara. Atul Shinde from Xilinx will be speaking about “Partitioning Hardware and Software Programmability for Best Carrier Ethernet Processing” on the first day of the conference, October 22, and I’ve stolen the following slide from his slide deck as a taste of what he’ll be discussing:

 

 Packet Processing Programmability Comparison.jpg

 

 

Shinde’s slide lists five major dimensions for the purpose of comparison:

 

  1. Description portability: You face extra work if you need to change your system description to fit the implementation hardware.
  2. Packet processing flow: If the implementation hardware does not match the natural flow required for packet processing, you face bottlenecks and resource conflicts.
  3. Lookup tables: Fixed-size memories in a hardware implementation lead to wasted resources and access conflicts.
  4. QoS policies: Poor implementation granularity leads to sub-optimal scaling and a lack of needed flexibility.
  5. Proprietary IP: If your packet processing requires anything special, you’ll incur additional hardware or suffer the inefficiency of software-based processing using NPUs or Multicore CPUs.

 

Don’t believe it? Register for the conference and make Shinde prove it to you.

 

Registration for pre-qualified attendees is free if registration forms are received by October 16, 2014. Registration for non-qualified attendees is $795 if received by that date. On-line registration closes on Thursday, October 16 at 5 PM Pacific.

 

Vivado 2014.3 adds more than 40 OpenCV functions from Auviz Systems

by Xilinx Employee ‎10-08-2014 01:26 PM - edited ‎10-09-2014 06:24 AM (1,438 Views)

The new Vivado Design Suite 2014.3 supports more than 40 OpenCV functions, now available from Xilinx Technology Ventures portfolio company and Xilinx Alliance Member Auviz Systems through Vivado HLS, the C-based synthesis tool in the Vivado Design Suite.

 

You can download Vivado Design Suite 2014.3 now, here.

 

More than 1400 people read last month’s blog post “JESD204B ADC interface magically commutates Gsamples/sec into a polyphase channelizer,” which described how ADCs with a JESD204B interface can commutate or decimate a Gsample/sec+ data stream into multiple lower-rate streams for parallel processing with a polyphase channelizer. If you understand that last sentence, then you will be delighted to learn that there is now a configurable Super Sample FIR filter in the latest release of the Xilinx System Generator, which you will find in the latest Vivado 2014.3 release.

 

 

Super Sample FIR Filter in Vivado 2014.3.jpg

 

Old joke from the original "Blues Brothers" movie: We have both kinds of music here—country and western.

 

The Zynq SoC gives you three major forms of programmability: software, hardware, and I/O. When you choose to use a Zynq SoC for the heart of a system, you get an expanded number of design choices—a very large design space to explore—and your real-time application’s performance depends on your team making the right choices in that design space. Xilinx has just posted a new 211-page document called “The UltraFast Embedded Design Methodology Guide” (UG1046) that will help your team make these choices using industry’s best design practices.

The User Guide dedicates chapters to:

 

 

UltraFast Embedded Design Methodology Guide.jpg

 

 

  • System-level design considerations
  • Hardware design considerations
  • Software design considerations
  • The hardware design flow
  • The software design flow
  • Debugging

 

It ends with a guide to additional Xilinx design resources.

 

The guide is free and is one click away. Click here.

Today’s release of the Vivado Design Suite 2014.3 for Xilinx 7 series All Programmable devices, Zynq SoCs, and UltraScale FPGAs includes a ton of enhancements and performance improvements. Here are a few:

 

  • If you’re looking for more performance, you’ll get significantly higher average Fmax from the new release.

 

  • If you want better QoR, you’ll see a substantial reduction in on-chip resource consumption for both RTL and HLS flows.

 

  • If you want faster runtime, you’ll find multi-core CPU support in Vivado 2014.3 and physical optimization is now multithreaded.

 

  • If you want easier AXI4 integration, you’ll find a fully automated way to connect different AXI4 flavors (memory-mapped versus streaming) by just wiring them together.

 

  • If you would like a more unified simulation environment, it’s there.

 

 

In addition, there’s a new UltraFast Embedded Design Methodology Guide, UG1046.

 

More detailed blogs about specific new features will follow shortly.

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I just found out that Doulos and EnSilica will be giving a free, 1-hour technical Webinar on October 10 to help you integrate your custom HDL IP into Xilinx Zynq SoCs so that the IP plays nice with the on-chip, dual-core ARM Cortex-A9 MPCore processors via the AXI interfaces. There are several convenient Webinar times during the day for India, Europe, and North America. Can’t beat the price--free. You have three days to register. Better hurry.

 

Register here, now.

Learn to debug and validate DDR3/DDR4 SDRAM designs in 1-day Keysight class, Oct 21 in Santa Clara

by Xilinx Employee ‎10-07-2014 02:49 PM - edited ‎10-07-2014 03:01 PM (1,047 Views)

Looking down the barrel of a DDR4-2400 or a fast DDR3 SDRAM design? Want some help? Keysight (formerly the T&M piece of Agilent) is giving a free, 1-day design seminar titled “Gain insight into DDR3/4 and LPDDR3/4 Signal Flow” in Santa Clara, California on October 21. This is a live class and promises to be well work a day of your time. It’s being taught by Jennie Grosslight, Keysight’s Memory Test Product Manager. I met her at DesignCon earlier this year. (See “Avoid the three pitfalls of designing with DDR4 SDRAM – Live from DesignCon 2014.”) If I was going to design a DDR4-baseed design, I’d want Jennie’s help. If you attend this class, you’ll understand why.

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About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.