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By Adam Taylor


In the previous MicroZed Chronicles blog post, we built a Zynq-based system with two PicoBlaze processor cores connected to the PS side of the Zynq via dual-port RAMS and BRAM (block RAM) controllers. In this post, we’ll look at how we can update the PicoBlaze processors’ programs stored in those dual-port RAMs.


The first aspect to look at is how we can store several PicoBlaze programs within a software application and then download them at will under the executing program’s control.


By Adam Taylor



In the previous instalment of the MicroZed Chronicles, we looked at the traditional method for updating and modifying PicoBlaze programs using the JTAG loader. The Zynq SoC’s PS (Processing System) provides additional capabilities that allow us to create a more flexible PicoBlaze program-loading system for a little more work. We can use the Zynq PS to access the BRAM memory on the Zynq SoC’s PL (Programmable Logic) where the PicoBlaze program resides. We will do this using the AXI BRAM controller. We explored the BRAM controller previously in the MicroZed Chronicles’ NeoPixel example.


This approach does require a little more manipulation because we cannot use the memory VHDL file generated by the PicoBlaze assembler. However, we’ll be using standard IP modules so it’s not significantly more difficult. Instead, we first create a dual-port RAM and initialize it with the contents of the hex file generated by the PicoBlaze assembler so that there will be an executable program in the PicoBlaze processor’s memory following power up.


The program we place in the dual-port RAM works no differently than the VHDL file generated by the assembler. However that program ran from a single-port memory. The addition of the second RAM port allows the ARM Cortex-A9 MPCore processors in the Zynq PS to access the shared, dual-port memory and overwrite the contents of that memory if required during development. This technique makes it easy to change the PicoBlaze processor’s executable program as required.


Spotted at this week’s SC14 (Supercomputing 2014) conference in New Orleans:



Invea-Tech HANIC-100G Live.jpg




I just had to stop at INVEA-TECH’s booth to find out more. Xcell Daily covered INVEA-TECH’s 100G PCIe card back in May during the Ethernet Technology Summit held in San Jose, CA (see “PCIe Gen3 essential for high-speed FPGA-based Ethernet adapter cards: INVEA-TECH”). The card is based on a Xilinx Virtex-7 H580T 3D FPGA. From that previous blog post:


“…the INVEA-TECH COMBO 100G HANIC accepts one 100Gbps CFP2 optical Ethernet transceiver module and the on-board Virtex-7 H580T 3D FPGA receives the Ethernet streams using four of its GTZ 28.05Gbps SerDes transceivers operating at 25Gbps to communicate with a CFP2 cage. The higher Ethernet data rates require an expansion to a PCIe Gen3 x16 host interface to handle the additional traffic bandwidth.”


In July of this year, INVEA-TECH in cooperation with CESNET announced successful transfer between an FPGA and host computer memory at a data rate exceeding 100Gbps through two PCIe Gen3 x8 blocks used as a x16 interface using Intel bifurcation technology.


Here at SC14 in New Orleans, INVEA-TECH was showing the card’s performance, which pretty much hits the theoretical performance limits, as you can see from this screen shot of the performance dashboard:



INVEA-TECH Performance Dashboard.jpg 


The SC14 demo and the dashboard above prove that the concept works.


For more details, see INVEA-TECH’s full report.

Convey Computer had a lot to say about HLL (high-level language) extensions and FPGA-based application acceleration at SC14 (Supercomputing 14) in New Orleans this week. Convey makes a line of FPGA-based hardware accelerator cards for PCIe computing and server systems including the Wolverine, which is based on a Xilinx Virtex-7 FPGA. Convey is one of several vendors offering COTS (commercial off-the-shelf) accelerator cards that are part of this week’s rollout of the Xilinx SDAccel Development Environment. (See “CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W.”)



Convey Computer Wolverine FPGA-based Accelerator Card.jpg 


Wolverine FPGA-based Application Accelerator for PCIe Systems



Convey’s booth at SC14 incorporated a very informative poster with a ton of good info about using HLL extensions to accelerate application code using FPGA-based boards. I’m going to quote a significant portion of that poster here, just in case you missed the Convey booth at SC14 or weren’t able to journey to New Orleans this week:



Alpha Data showcases PCIe accelerator card for HPC based on Kintex UltraScale FPGA at SC14

by Xilinx Employee ‎11-20-2014 08:28 AM - edited ‎11-20-2014 08:38 AM (674 Views)

One of the three key components in this week’s Xilinx SDAccel Development Environment announcement at SC14 (Supercomputing 14) in New Orleans is the availability of COTS (commercial off-the-shelf) accelerator cards for HPC (high-performance computing) applications. Alpha Data’s ADM-PCIE-7V3 FPGA accelerator board based on a Xilinx Virtex-7 VX690T FPGA is one of the COTS accelerators directly supported in the initial SDAccel release and this card was on display in action at SC14 in the Xilinx booth. One aisle over in the Alpha Data booth, you could see the company’s next-generation ADM-PCIE-KU3 accelerator card based on a Xilinx Kintex UltraScale FPGA. Here’s a photo of the card from SC14:



Alpha Data ADM-PCIE-KU3 FPGA Accelerator Board.jpg


I’ve been writing about the Micron HMC (Hybrid Memory Cube) for a while and today saw one live and in action at the Micron booth here at SC14 (Supercomputing 14). The HMC memory was accepting writes at 21 or 22Gbytes/sec and handling simultaneous reads, also at approximately 21 or 22Gbytes/sec. (It’s amazing how casually we’re treating a Gbyte/sec of unidirectional memory bandwidth—plus or minus—in this video. After all, what’s a Gbyte/sec of memory bandwidth among friends?)


In this demo, an Open-Silicon HMC controller instantiated in a Xilinx Virtex UltraScale VU095 FPGA on a Xilinx VCU109 Evaluation Board used sixteen UltraScale SerDes ports to operate one HMC link between the FPGA and the HMC at 15Gbps per line to achieve these stratospheric rates. (There are 16 high-speed serial lines per HMC link and you can use multiple links to connect to an HMC memory for really awesome memory bandwidth.)


Image-processing, computer vision, and linear algebra libraries from Auviz Systems are key elements in the Xilinx SDAccel Development Environment rolled out this week at SC14 (Supercomputing 14) in New Orleans. (See “CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W.”) Nagesh Gupta, Founder and CEO of Auviz, gave me the following 2-minute tour of his company’s product:






As you can see from the video, Auviz libraries help SDAccel deliver GPU-like performance with significantly less power by harnessing FPGA hardware acceleration in a way that’s friendly to the software programming world.



If you’re interested in working with the Micron HMC (Hybrid Memory Cube), then you’ll likely be interested in openHMC—an open-source, AXI4-compliant memory controller for the HMC developed by the Computer Architecture Group at the University of Heidelberg in Germany. It’s a parameterizable IP block that allows you to set different overall data widths, external lane widths, and clock speeds depending on application needs. Micron was exhibiting an HMC board connected to a Xilinx UltraScale FPGA eval board implementing the open-source HMC controller in its booth at SC14 (Supercomputing 14) in New Orleans.



Open-Source HMC Controller IP for UltraScale.jpg



The openHMC memory controller implements the following features as described in the HMC specification Rev 1.1:


  • Full link-training, sleep mode, and link retraining
  • 16- to 128-byte read and write (posted and non-posted) transactions
  • Posted and non-posted bit-write and atomic requests
  • Read and Write Mode
  • Full packet flow control
  • Packet integrity checks (sequence number, packet length, CRC)
  • Full link retry


Currently the following configurations are supported (8 or 16 lanes):


  • 2 FLITs per Word / 256-bit datapath
  • 4 FLITs per Word / 512-bit datapath
  • 6 FLITs per Word / 768-bit datapath
  • 8 FLITs per Word / 1024-bit datapath


For more information and a free Verilog download of the open-source IP, click here.

Dini Group SC14 Booth Sign.jpgDini Group has been cranking out several types of boards for HPC (high-performance computing), ASIC emulation, and networking applications using many generations of Xilinx FPGAs. The sign appearing on the right, spotted at the Dini Group’s booth at SC14 (Supercomputing 2014) in New Orleans clearly indicates that yet another board is on the way, based on the latest-generation Xilinx UltraScale architecture. The Web site lists boards based on both Virtex UltraScale and Kintex UltraScale devices.




This week at SC14 (Supercomputing 14) in New Orleans, Pico Computing unwrapped its Trifecta workstation concept for HPC (high-performance computing). Pico Computing’s Trifecta melds three key HPC technologies—a Xilinx Virtex UltraScale FPGA, Micron’s category-busting HMC (Hybrid Memory Cube), and OpenCL—to create a supercomputing platform with an air-cooled, PC footprint. The heart of the Trifecta platform is this board, which debuted in the Pico Computing and Xilinx booths at SC14:



Pico Computing UltraScale FPGA HMC Board.jpg



The large silver square on the left is a Xilinx Virtex UltraScale VU095 FPGA, which started shipping in May, 2014. (See “Xilinx ships first 20nm Virtex UltraScale FPGA – Why this matters to you.”) On the right, you see four smaller silver rectangles; these are the Micron HMC memories. The board has sites for as many as eight HMCs. The HMCs communicate with the Virtex UltraScale FPGA over multiple 15Gbps lanes. HMC memories operate as much as 15x faster while consuming 70% less energy when compared to DDR3 SDRAMs, delivering as much as 240Gbytes/sec of bidirectional bandwidth over high-speed serial links.


The third winning technology in Pico Computing’s Trifecta is OpenCL, which allows application developers to exploit the superior performance/watt of FPGA hardware acceleration while continuing to use a familiar software-development environment.


According to this week’s press release from Pico Computing, the Trifecta platform will be available in beta version in the first quarter of 2015.

SDAccel for direct OpenCL, C, C++ to FPGA hardware acceleration demo at SC14—the video

by Xilinx Employee ‎11-19-2014 06:23 AM - edited ‎11-19-2014 06:27 AM (792 Views)

Earlier this week, Xilinx announced the SDAccel Development Environment for OpenCL, C, and C++, which delivers as much as 25X better performance/Watt to the data center using FPGA-based hardware acceleration. The announcement was timed for the SC14 (Supercomputing 2014) conference in New Orleans where SDAccel is being demonstrated all week in the Xilinx booth. Here’s a short video of Kamran Khan, a Technical Marketing Manager at Xilinx, who captures the basic idea behind SDAccel in less than two minutes:







For more information on the new Xilinx SDAccel Development Environment, see “CPU/GPU-like software development environment for OpenCL, C, C++ delivers FPGA-based app acceleration with 25x better performance/W.

Last month, Intilop announced availability of a TCP Hardware Accelerator (a TCP Offload Engine or TOE) that could handle 16K concurrent TCP sessions. The Intilop TCP accelerator is available pre-ported and tested on an Alpha Data ADM-PCIE-7V3 card, which I caught in action this week in the Xilinx booth at SC14 (Supercomputing 14) in New Orleans. The Alpha Data ADM-PCIE-7V3 card is based on a Xilinx Virtex-7 VX690T FPGA. Kelly Masood—founder, president, and CTO of Intilop—demonstrated the TOE accelerator for me.


Today was the first day that the exhibit hall opened at SC14 (Supercomputing 2014) in New Orleans and the Xilinx booth was filled with demos. Xilinx Data Center Architect Shreyas Shah quickly ran me through three of the demos:



  • FPGA fast Key Value Store
  • FPGA 25G Ethernet Mac
  • FPGA-based NVMe storage controller



The new Xilinx SDAccel Development Environment gives data center application developers the complete FPGA-based application acceleration they want, with a software-defined, CPU/GPU-like development experience and 25x better performance/W. SDAccel includes a fast, architecturally optimizing compiler that makes efficient use of on-chip FPGA resources; a familiar software-development flow with an Eclipse-based Integrated Design Environment (IDE) for code development, profiling, and debugging, which provides a CPU/GPU-like work environment; and dynamic reconfigurable accelerators optimized for different data center applications that can be swapped in and out on the fly. Applications can have many multiple kernels swapped in and out of the FPGA during runtime without disrupting the interface between the server CPU and the FPGA for nonstop application acceleration.



SDAccel Development Environment Matrix.jpg




The SDAccel compiler supports source code using any combination of OpenCL, C, C++, Kernels, and targets high-performance Xilinx FPGAs. The SDAccel compiler delivers as much as a 10X performance improvement over high-end CPUs and one tenth the power consumption of a GPU, while maintaining code compatibility and a traditional software programming model for easy application migration and cost savings. Based on partner benchmarks, the SDAccel compiler provides 3X the performance and resource efficiency of competitive FPGA solutions. The automatically generated designs from the SDAccel compiler can even deliver more performance than hand-coded RTL design solutions—as much as 20% in some cases.


Developers can use a familiar workflow to optimize their applications and take advantage of FPGA platforms with little to no prior FPGA experience. The IDE provides coding templates and SW libraries and enables compiling, debugging, profiling, and FPGA emulation on x86 platforms. When ready for deployment, it then implements the algorithm on data-center-ready COTS FPGA platforms complete with automatic instrumentation insertion. Data-center-ready acceleration boards are available from Convey Computer, Alpha Data Parallel Systems, and Pico Computing. More COTS partners will be added early in 2015.


SDAccel libraries include built-in support for OpenCL plus DSP, Video, and linear algebra libraries for high-performance, low-power implementations. Xilinx Alliance member Auviz Systems provides optimized, domain-specific OpenCV and BLAS libraries for SDAccel.


Application developers can start to use SDAccel entirely in the x86 emulation space to get their code functional. When they are confident of their algorithms, they can profile the code to find code sections that would benefit from acceleration. Developers can then take these targeted sections and seamlessly use fast, automatically generated, cycle-accurate simulations of the kernels to debug and optimize the hardware acceleration while still working at an architectural level. No FPGA is needed during these first two phases. Once proven, the application is then ready to port to the host/FPGA system. The SDAccel Development Environment supports all of these activities from a single, programmer-friendly cockpit.


SDAccel offers the only FPGA-based dynamic reconfigurable accelerators that enable real-time CPU/GPU-like run-time updates. Unique to FPGA-based hardware-acceleration solutions, SDAccel keeps the system functional during kernel updates with the only FPGA-based dynamic reconfigurable capability that can load new hardware accelerator kernels—similar to the abilities of CPU/GPU accelerators—while keeping critical system interfaces and functions such as memory, Ethernet, PCIe, and performance monitors live. This on-the-fly system reconfiguration is ideal for immediate updates to data center compute needs and loads. An example of an application where this ability is of strategic advantage: switching between image search, video transcoding, and image processing on the fly.


All of this translates into resource optimization through hardware reuse, which is a significant advantage in data center environments. In simple terms, an SDAccel-based system can accelerate one application today and if another type of acceleration is needed tomorrow, the system can be upgraded quickly and smoothly.


For more information on the new Xilinx SDAccel Development Environment, click here. If you are attending SC14 (Supercomputing 2014) this week in New Orleans, visit the Xilinx booth (#3903 and #4003) where you’ll be able to see SDAccel in action.




Low-latency 25G Ethernet MAC and PCS IP for FPGAs on stage next week at SC14 in New Orleans

by Xilinx Employee ‎11-14-2014 01:53 PM - edited ‎11-14-2014 01:59 PM (1,132 Views)

25G Ethernet Consortium Logo.jpgThe new Xilinx low-latency 25G Ethernet MAC and PCS IP will be demonstrated in the Xilinx booth at next week’s SC14 (Supercomputing 2014) conference in New Orleans. Bumping Ethernet bandwidth from 10G to 25G improves performance and increases front-panel bandwidth for TOR (top-of-rack) switches and other network equipment by 2.5x, which is no small deal. The Xilinx low-latency 25G Ethernet MAC and PCS IP supports the new 25G Ethernet Consortium spec.




Industrial power, control, and communications applications for FPGAs and the Zynq SoC will overflow the Xilinx booth (Hall 4 #169) in Nuremberg this coming November 25-27 at the SPS/IPC/Drives show. The following Xilinx Alliance members and Xilinx will be showing these advanced industrial applications:


  • QDESYS: High-performance silicon carbide multilevel power inverter with low THD, high ratio power/volume, three-level modulation with very low EMI, low switching loss, and ultra-fast control loops
  • QDESYS: EtherCAT fast electric drive with an embedded EtherCAT slave controller IP core from Beckhoff GmbH
  • Silicon Software: Embedded computer vision for intelligent stations showcasing high-speed image processing and safe recognition of inspected objects
  • HMS: Anybus support of all major Fieldbus and industrial Ethernet communications using the Zynq SoC
  • ZHAW School of Engineering: Hardware accelerated Profinet implementation in an FPGA allows full bandwidth utilization of Fast Ethernet (100 Mbit/s)
  • SoC-e: zero-loss switchover in a high-availability cyber-physical system using HSR/PRP (High-Availability Seamless Ring, Parallel Redundancy Ring) IP and IEEE1588-2008
  • Xilinx: a safety-oriented motor control system for functional safety systems based on dual-core, lockstep processors implemented in an FPGA




10G, 16K concurrent TCP/UDP sessions, 95% bandwidth, 1 FPGA—see it at SC14 next week in New Orleans

by Xilinx Employee ‎11-14-2014 08:36 AM - edited ‎11-14-2014 08:36 AM (782 Views)

Three weeks ago, Intilop announced availability of a TCP Hardware Accelerator (a TCP Offload Engine or TOE) that could handle 16K concurrent TCP sessions. The Intilop TCP accelerator is available pre-ported and tested on an Alpha Data ADM-PCIE-7V3 card, which you can see in action next week in the Xilinx booths (#3903 and #4003) at SC14 (Supercomputing 14) in New Orleans. The Alpha Data ADM-PCIE-7V3 card is based on a Xilinx Virtex-7 VX690T FPGA. For more information, see “Intilop’s FPGA-based TCP Hardware Accelerator manages 16K concurrent TCP sessions.”


You will also be able to see the following data center and HPC (high-performance computing) demos in the Xilinx booths:


  • Key Value Store Acceleration
  • NVMe Flash Storage Platform
  • Low Latency 25G/50G Ethernet MAC
  • Various software-defined development environments



If you’re at SC14, be sure to stop by the booths of various Xilinx Alliance program members for more interesting demos:


  • Alpha Data – Booth #3803: industry-leading FPGA accelerator boards for network processing
  • Auviz Systems – Alpha Data Booth #3803: computer vision and image processing middleware IP
  • Convey Computer – Emerging Technology Booth ET11: Wolverine line of high performance coprocessors
  • The Dini Group – Booth #528: scalable Kintex-7 and Virtex-7 FPGA-based solutions for HPC applications
  • Invea-Tech – Booth #3923: world's first HPC 100GE transmit/receive data stream on xR4 PCIe cards
  • Micron – Booth #1949: HMC interoperability demos on Xilinx Virtex UltraScale devices
  • Nallatech – Booth #1332: high performance computing and network processing
  • Pico Computing – Booth # 3233: HMC operation on Xilinx Virtex UltraScale devices and a software-defined development environment

Want to see video from your cable box, satellite box, over-the-top video box, tablet, phone, game box, or Blu-ray player all at once? The Zynq-based SkreensTV, a new IndieGoGo project, mashes up HDMI and wireless video sources onto one configurable HD-ready screen for $399—but for a limited time only, that’s the pre-order price!


Video sources include five HDMI inputs, Wi-Fi, Bluetooth, 10/100/1000 Ethernet, and two USB ports to connect cable/satellite/IPTV set-top boxes, gaming consoles, laptops and any other streaming devices such as Apple TV, Chromecast, and Roku to your TV. You control the SkreensTV box wirelessly with a tablet or a smartphone running the appropriate iOS or Android app. On-board Flash provides for some local storage. SkreensTV systems are available with 4, 32, or 64Gbytes of storage ($399/$499/$599). All of this is managed by a Xilinx Zynq SoC, which provides significant video-processing abilities and integration to the project as well as the programmability needed to enable the creation of additional applications to run on the unit. (There’s a Developer’s Program.)





Sad to say, you’re not getting one of these boxes for the Winter holidays this year. First, this project needs funding and the goal is set high: $200,000. Assuming the funding drive succeeds, early SkreensTV shipments are scheduled for September, 2015. However, the IndieGoGo funding period for this project turns into a pumpkin at midnight (Pacific Time) on December 13, 2014, so you need to pledge now to get the introductory pricing.


LDPC FEC for wireless backhaul achieves significant SNR gain with a low number of iterations

by Xilinx Employee ‎11-13-2014 03:52 PM - edited ‎11-13-2014 04:00 PM (611 Views)

There’s an LDPC FEC (low-density parity check forward error correction) module embedded in the Xilinx 1.6Gbps small cell backhaul modem announced earlier this year. If you’d like to see some operational details of this FEC, there’s a new article written by Tarmo Pihl, director of wireless backhaul business at Xilinx, titled “LDPC FEC is becoming the preferred technology in wireless backhaul” that was just posted on the Embedded Computing Design Web site. LDPC codes are linear with a sparse parity check matrix. They belong to the class of block codes designed to include low density "ones" in rows and columns of the parity check matrix.


These codes have seen increasing use in communications applications since the development of the DVB-S2 satellite broadcasting standard back in 2003. Use of LDPC FEC instead of convolutional coding for DVB increased threshold gains by roughly 3dB and enabled migrating to higher spectral efficiency. The special X-decoding algorithm used in Xilinx's FEC code achieves significant SNR gain with a low number of iterations, which in turn results in better decoder latency.



EVT RazerCam Small.jpgFor the month of December, you can get the 640x480-pixel version of the EVT RazerCam smart camera for machine-vision applications—which is based on the Xilinx Zynq SoC—along with EVT’s EyeVision 3.0 Standard version image-processing software for €1850. That’s normally the price for just the software, you you’re getting the camera at no additional cost. Normally, the RazerCam smart camera sells for €1160 so the month-long special price represents a considerable savings.



For more information about the EVT RazerCam and EyeVision software, see “New Zynq-based RazerCam is one smart industrial machine vision camera with three different sensor options.”

If you are working with high-performance, broadcast-quality video then you are undoubtedly familiar with the SGI interface standard. Now you can snap a 6-port SDI mezzanine board onto any of several Xilinx All Programmable device evaluation and development boards including the Xilinx KC705 for the Xilinx Kintex-7 XC7K325T FPGA, VC707 for the Xilinx Virtex-7 XC7VX485T FPGA, VC709 for the Xilinx Virtex-7 XC7VX690T FPGA, KCU105 for the Xilinx Kintex UltraScale XCKU040 FPGA, and ZC706 for the Xilinx Zynq XC7Z045 All Programmable SoC. The inrevium TB-FMCH-12GSDI 6G/12G-SDI FPGA Mezzanine Card provides one SDI input port, one SDI output port, three SDI input/output ports, and one SDI video sync input port. The board’s FMC connector employs a stackable design that allows you to double the number of input, output, and input/output ports with an expansion card. The 6G/12G-SDI FPGA Mezzanine Card card will be available early next year from inrevium and from Fidus in North America. FPGA reference designs using this board will also be available.




inrevium TB-FMCH-12GSDI 6G-12G-SDI FPGA Mezzanine Card.jpg 



Xilinx President and CEO Moshe Gavrielov discusses TSMC 16nm FinFET Plus (16FF+) Production Milestone

by Xilinx Employee ‎11-12-2014 02:19 PM - edited ‎11-12-2014 03:39 PM (662 Views)

TSMC announced today that its 16nm FinFET Plus (16FF+) process, an enhanced version of TSMC’s 16FF process, is now in risk production. Depending on the IC design, TSMC’s 16FF+ process operates 40% faster than the company’s planar 20nm system-on-chip (20SoC) process or consumes 50% less power at the same speed. The TSMC announcement also lists seven semiconductor customers for the 16FF+ process—including Xilinx. Here’s a quote from Moshe Gavrielov, President and CEO of Xilinx, taken from today’s press release:


"TSMC is once again demonstrating their leadership in the industry by delivering their 16FF+ process with exceptional results. This risk production milestone achievement and our continued close collaboration is enabling Xilinx to realize the industry’s highest FPGA performance per watt and an unprecedented level of programmable systems integration with the industry’s first All Programmable MPSoC and 3rd Generation 3D ICs.”


AMC (Advanced Mezzanine Card) FPGA Carrier from VadaTech based on Zynq SoC

by Xilinx Employee ‎11-12-2014 01:25 PM - edited ‎11-12-2014 01:46 PM (541 Views)

VadaTech AMC518 AMC FPGA Carrier for FMC photo.jpgThe Zynq-based VadaTech AMC518 is an AMC FPGA Carrier for FMC per VITA 57. The AMC connector complies with the AMC.1, AMC.2 and/or AMC.4 specification and supports several communications protocols including PCIe, SRIO, and XAUI via FPGA reprogramming. The on-board Xilinx Zynq XC7Z045 SoC is paired with a 32-bit DDR3 SDRAM bank on the processor side and 64-bit DDR3 SDRAM on the PL (Programmable Logic) side for ample buffer space. The Zynq SoC also interfaces directly to the AMC card’s FCLKA, TCLKA-D, FMC DP0-7 and all FMCLA/HA/HB pairs.





VadaTech AMC518 AMC FPGA Carrier for FMC .jpg




How to fit a 10-pound design into a 5-pound All Programmable FPGA (or 10kg in a 5 kg FPGA)

by Xilinx Employee ‎11-12-2014 11:12 AM - edited ‎11-12-2014 12:55 PM (545 Views)

The Xilinx UltraScale architecture delivers a 2x increase in routing capacity and tighter logic packing to help you fit a 10-pound design into a 5-pound FPGA (or 10kg in a 5 kg FPGA) while meeting all of your design constraints. You get high device utilization with superior performance because of these UltraScale features:


  • Increased local interconnect that minimizes the routing-delay problem in large FPGAs
  • ASIC-like clocking that optimizes clock skew and deploys clocks only where needed
  • CLB enhancements that improve logic packing by allowing partially used logic cells to be filled with additional design logic


When managed by the Xilinx Vivado Design Suite tools, these UltraScale features have a significantly beneficial effect when you’re trying to fit your design into the smallest possible FPGA with the slowest possible speed grade to shave system costs. (When aren’t you?)


Here’s a 10-minute video that elaborates on all of these concepts:





Getting the Most out of Your PicoBlaze Microcontroller

by Xilinx Employee on ‎11-11-2014 03:03 PM (595 Views)


By Adam P. Taylor, Head of Engineering – Systems, e2v



The PicoBlaze is a compact 8-bit soft-core microcontroller that FPGA engineers instantiate within their selected Xilinx FPGA. Once implemented, this core is completely contained within the FPGA fabric using only logic slices and Block RAMs; it requires no external volatile or nonvolatile memory.


Thanks to its small implementation footprint, it is possible for an FPGA to contain multiple PicoBlaze instantiations, with each instantiation used to implement control structures typically created by state machines. The result is a reduction in the development time along with a standardized approach to control structure generation. Thanks to the underlying high performance of the Xilinx FPGA fabric, PicoBlaze instantiations are often capable of outperforming many discrete 8-bit microcontrollers.


Let’s take a look at how we can best utilize this handy device within our designs.


A Framework for FPGA Design Planning

by Xilinx Employee on ‎11-11-2014 10:30 AM (603 Views)


By Jeffrey Lin, Global Communications Services Group, Xilinx


The Xilinx Global Communications Services Group has long been using a time-proven design framework to develop and deliver turnkey FPGA designs to Xilinx customers for products ranging from medical-imaging processing engines to self-learning network switch engines. It is a framework we have developed and evolved over the course of designing, developing and delivering hundreds of FPGA designs.


The framework we use covers everything from system architecture considerations to FPGA development and test planning. Let’s take a closer look at this framework, with a focus on the FPGA hardware, in hopes that other engineering teams might find it a useful tool for tackling complex FPGA design projects of their own.


Efficient Parallel Real-Time Upsampling with Xilinx FPGAs

by Xilinx Employee on ‎11-10-2014 04:21 PM (483 Views)


By William D. Richard, Associate Professor, Washington University, St. Louis


Upsampling is required in many signal-processing applications. The easiest way, conceptually, to upsample a vector of data by a factor of M is to zero-pad the discrete Fourier transform (DFT) of the data vector with (M-1) times as many zeros as there are actual frequency components and then transform the zero-padded vector back into the time domain. This approach is computationally expensive, however, and does not lend itself to efficient implementation inside FPGAs. The efficient, parallel, real-time upsampling circuit presented here produces M upsampled values per ADC clock, where M is the desired upsampling factor. Our Xilinx Virtex-6 XC6VLX75T FPGA implementation, which upsamples by a factor of M=4, serves as an example of the more general technique.


FPGAs Aid Search for Dark Energy with CHIME Telescope

by Xilinx Employee on ‎11-10-2014 02:43 PM (466 Views)


By Steve Leibson, Editor in Chief, Xcell Daily


A mysterious force is causing the universe to expand at an ever-increasing rate. Physicists don’t really know what it is but they have named it: dark energy. There’s no known way to directly detect dark energy experimentally. Evidence is strictly indirect. Observing and measuring periodic fluctuations in the distribution of baryonic matter, specifically neutral hydrogen, across hundreds of millions of light years may be among the best methods we have for studying dark energy. These variations, called baryonic acoustic oscillations (BAO), serve as a “standard ruler” for cosmological distance. A group of researchers based at universities in Canada are developing a radio telescope purpose-built for measuring BAO at the Dominion Radio Astrophysical Observatory in the heart of Canada’s wine country on the south end of Okanagan Lake in British Columbia.


This telescope, called the Canadian Hydrogen Intensity Mapping Experiment (CHIME), reconstructs an image of the overhead sky without having to point at a specific direction. The telescope processes the signals received across a large array of radio antennas using a technique called interferometry. Historically, most interferometry telescopes have reconstructed images across a small region of the sky by mechanically steering several antennas, each in its own telescope dish, to point at that region. CHIME has no moving parts, so it may be thought of as a digital telescope. It reconstructs an image of the entire overhead sky by digitally processing the information its antennas have received as the Earth rotates through a 24-hour period. A Xilinx Kintex-7 FPGA is a key component.


Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

by Xilinx Employee ‎11-10-2014 09:45 AM - edited ‎11-10-2014 09:46 AM (872 Views)


By Adam Taylor


So far we have looked at how we could instantiate the Xilinx PicoBlaze processor hardware within a system based on the Zynq SoC. In this blog, I am going to explore more on how we generate the PicoBlaze program and how we can update the program using the JTAG port without recompiling the design.


4K TV Development Made Easy

by Xilinx Employee on ‎11-07-2014 03:14 PM (827 Views)


By Roger Fawcett, OmniTek


Society of Motion Picture & Television Engineers (SMPTE) standards for 6-Gbps and 12-Gbps SDI, supporting 4K60 video, are only just being released, while HDMI 2.0 and DisplayPort supporting the same resolution are in the early stages of adoption. Given the significant consumer demand for 4K UHD TVs, many ad hoc standards have rushed in to fill the void. Indeed, so much about 4K UHD TV is in a state of flux that it is essential for systems to be flexible enough to adapt to the developing standards. The way to ensure flexibility is to replace the time-honored chip sets and ASSPs long used for these designs with All Programmable devices including Xilinx FPGAs and the Xilinx Zynq SoC. These solutions offer the flexibility needed while also delivering performance comparable to that of ASICs. Xilinx offers a lot of help for 4K TV designers—all at a much lower cost in both time and money than designing your system from scratch.


About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.