If you’re developing large IP blocks, then S2C has something to help you accelerate development: the AXI-4 Prototype Ready Quick Start Kit based on the Xilinx Zynq SoC and Xilinx Virtex-7 2000T 3D FPGAs. The Quick Start Kit couples a Xilinx Zynq ZC702 Evaluation Board to an S2C TAI Logic Module as showing in the following diagram:
The Xilinx ZC702 Evaluation Board has an on-board Zynq Z7020 SoC with a dual-core ARM Cortex-A9 MPCore processor and a programmable logic capacity of 85K logic cells—equivalent to approximately 1.3M gates. The S2C Quick Start Kit expands this capacity by extending the Zynq SoC’s AXI-4 bus through an interface module to one or more external Xilinx Virtex-7 2000T 3D FPGAs on the S2C TAI Logic Module. Each Virtex-7 2000T FPGA has a capacity of 1,954,560 logic cells—a 23X expansion in programmable-logic capacity per FPGA. This added programmable-logic capacity allows designers to quickly leverage a production-proven, AXI-connected prototyping platform with a large and easily scaled logic capacity – all supported by a suite of prototyping tools from S2C.
A demonstration of the Kit will be shown at the S2C booth at ARM TechCon 2014 in Santa Clara, CA on October 1-3.
Note: For more information about S2C’s prototyping tools, see the Xcell Daily blog post “TAI Player Pro 5.1 prototyping tool automatically partitions very large designs across multiple Virtex-7 3D FPGAs.”
This week’s ARM TechCon in Santa Clara at the convention center. On Thursday at 11:30am, we’ll be tearing down two very interesting Zynq-based products on the exhibit floor. I suspect you won’t want to miss the event because I know there will be design tips galore revealed during these teardowns.
First, we’ll be pulling the covers off of the National Instruments VirtualBench, a many-instruments-in one-box product. (Something I’ve wanted to do ever since the product was announced a year ago.) The NI VirtualBench incorporate the features of a mixed-signal oscilloscope, function generator, logic analyzer, DMM, programmable dc power supply, and a set of programmable digital I/O control lines in one compact package that won’t consume very much bench space. The NI VirtualBench uses either a PC or a Tablet as its user interface.
National Instruments VirtualBench
The second product we’ll open up is the Cloudium Integrated Media Processing Platform, a fanless video compression/decompression box designed to move HD video and audio bidirectionally through the Internet and through the cloud with maximum efficiency. The box we’ll be opening up is called the Cloudium Systems Zero Client and the Zynq SoC inside the box provides flexibility that allows users to upgrade to new protocols easily without opening the box. But we’re going to open it anyway.
Cloudium Systems Zero Client
By Adam Taylor
In the last blog we looked at sharing data between the Zynq SoC’s two ARM Cortex-A9 MPCore processor. I noted that the approach used could have been improved—made more efficient—had we used software interrupts to communicate between the two cores.
Each ARM Cortex-A9 processor core in the Zynq SoC has 16 software-generated interrupts. Each processor can use these interrupts to interrupt itself, to interrupt the other processor core, or to interrupt both cores. For this example, we will use Core 0 to generate an interrupt that informs Core 1 that there has been an updated LED pattern received.
Using software interrupts is not too different from using hardware interrupts except of course in how we trigger them.Read more...
AMP—asymmetric multiprocessing—is a way to extract significant work from the two ARM Cortex-A9 MPCore processors on the Xilinx Zynq All Programmable SoC. Avnet’s Ron Wright is currently touring the world with his AMP-for-Zynq X-fest class titled “Using Operating Systems on Zynq.” I learned a lot in this class and can highly recommend it.
Early in the class, Wright said “Until recently, AMP and SMP systems were ad hoc. Now there’s a framework.” VMware has been providing desktop virtualization using a hypervisor for a while, but embedded systems—particularly embedded systems for Zynq with its programmable logic capabilities—need something else, said Wright. They need paravirtualization, which restricts the number of OS calls providing a consistent emulation layer that hides the changing FPGA hardware beneath. As a result, the guest OS needs to know that it’s been virtualized.
Where does that paravirtualization come from? Virtio is the framework of choice for embedded Linux. Because we now have Virtio, embedded developers now increasingly use Linux as an embedded hypervisor.
Linux is the hypervisor.Read more...
RS Components distributes the Zynq-based Red Pitaya open-source measurement and control SOM board. Back in April, RS published an interview with unspecified members of the Red Pitaya design team. The answers to the questions are valuable for anyone considering the Zynq SoC for a design.Read more...
During the ECOC 2014 Exhibition held in Cannes this week, several members of the OIF Physical and Link Layer (PLL) Working Group including Xilinx demonstrated multi-company interoperability of the OIF CEI-28G-VSR and CEI-25G-LR interfaces. The demonstrations covered optical and active copper interoperability, ranging from the emerging CFP4 MSA using the OIF CEI-28G-VSR electrical specification to long-reach backplane and QSFP28 passive copper cable using the OIF CEI-25G-LR electrical specification.Read more...
What a difference a day can make. The Zynq Book is now #1 on the Amazon Microprocessor and System Design list and #2 on the Amazon Logic Circuits book list. Order the book on Amazon or click here to find out how you can download a free PDF of the book.
Electronics Weekly in the UK recently published an article about agile design written by Martin Keenan, head of applications strategy at RS Components, that I found quite interesting and well worth a blog. Keenan wrote:
“Giving engineers everything to do a prototype quickly, easily and at no cost is the basis of a good design strategy… The ‘Rapid Concept and Prototyping’ approach can enable significantly lighter up-front requirements: the end goal can be considerably looser with ‘must-have’ functionality identified at a much higher level, allowing entire engineering departments to be involved in brainstorming. Multiple concepts can be created digitally and developed in parallel with the strongest concepts progressed and the weakest quickly abandoned in an evolutionary and iterative process. Physical prototypes can be produced, quickly followed by customer and market testing, with a small number of prototypes taken on through the full design process.”
First, I think Keenan’s observations are spot on for today’s world. Design speed and time to market are a big part of the game in a globally competitive environment. There are lots of people around the world who have great ideas so implementation is a significant differentiator. And although the term “agile” is most often used and an adjective for software development, it very much applies to hardware development as well.
Note: RS Components distributes a very interesting Zynq SOM called the Red Pitaya, which has a beefed-up ADC and DAC combo. See the Xcell Daily Blog post “Zynq-based Red Pitaya Open Instrumentation Platform blows past $50K Kickstarter funding goal by 5x."Read more...
ARM TrustZone technology is a system-wide approach to system security and is directly applicable all sorts of secure tasks including payment protection, digital rights management, and secured enterprise solutions. Add IoT applications to that list too. TrustZone technology is tightly integrated into ARM Cortex-A processors including the two ARM Cortex-A9 MPCore processors on the Xilinx Zynq SoC. The secure state is also extended throughout the system via the AMBA AXI bus through an additional control bit for each of the read and write channels on the main system interconnect. ARM TrustZone technology support permeates the Zynq SoC’s PS (processor system) and PL (programmable logic) sections.
For more information on the use of ARM TrustZone technology in Xilinx Zynq SoCs, see the White Paper “TrustZone Technology Support in Zynq-7000 All Programmable SoCs.”
There’s not a trace, not a shred of information about FPGAs or Zynq SoCs in the following Jack Ganssle video but the information should prove invaluable to anyone developing embedded systems based on the full range of Xilinx All Programmable devices. I see this trick as especially applicable for systems based on the Zynq SoC but also useful for a wide range of embedded designs that include Xilinx devices.
In less than five minutes, Jack will show you how to configure a $25 Radio Shack analog multimeter as a system idle-time indicator that gives you a highly visual indication of how much time your design spends doing nothing.Read more...
A new Xilinx App Note, XAPP1188—FPGA Configuration from SPI Flash Memory using a Microprocessor, tells you how to use the same EEPROM to hold your processor’s boot code and your FPGA’s configuration bitstream. This approach obviously reduces component count and you can implement this idea using as few as two SPI pins: MISO and SCLK. The application note describes several scenarios using two pins and up. One of them just might fit your needs.
You will be able to boost 1U front-panel bandwidth on network switching gear from 1.6Tbps to 4.4Tbps by switching from 100Mbps CFP4 optical modules to modules based on the new 400Gbps CDFP 2.0 specification. This new spec—just announced today by the CDFP Multi-Source Agreement (MSA)—defines a 400Gbps port using 16 lanes operating at 25Gbps each. The CDFP 2.0 specifications apply to direct-attach cables, active optical cables, and connectorized optical modules. The spec document also covers signal integrity, thermal cooling, and EMI protection for hot-pluggable modules.
The key advantages conferred by the 400Gbps CDFP 2.0 specification are the obvious quadrupling of port bandwidth for high-speed network connections and the more subtle but no less important densification of the 1U front panel, which can now handle nearly three times the bandwidth by replacing sixteen 100Gbps CFP4 modules with eleven 400Gbps CDFPmodules, as shown below.
For more information, see the White Paper, “CDFP MSA Delivers 400 Gb/s Today.”
CDFP MSA founder-promoters include: Avago Technologies, Brocade Communications, IBM Corporation, JDS Uniphase, Juniper Networks, Molex Incorporated, and TE Connectivity. Contributing member companies include: FCI, Finisar, Huawei, Inphi, Ixia, Mellanox Technologies, Nextron, Oclaro, Semtech, Sumitomo Electric, Xilinx, and Yamaichi Electronics.
Adapteva’s open-source Parallella supercomputing development board based on the Xilinx Zynq SoC, was a Kickstarter project that raised $898,921 in late 2012. Adapteva says it has now shipped more than 10,000 boards. Applications for this board include:
The Parallella board includes a Zynq Z7010 SoC and an Adapteva Epiphany multicore processor chip with 16 parallel computing cores.Read more...
Next week is ARM TechCon in Santa Clara, California. If you’re using ARM processors, you need to be there. If you’re using or thinking about using the ARM-based Zynq All Programmable SoC from Xilinx, I’ll be doing two Zynq-based product teardowns on the expo floor on October 2 in the morning at 11:30am. (See “Teardown Thursday @ ARM TechCon: What’s In There Besides Zynq?”)
According to a Google+ posting by UBM, you can get a free ARM TechCon expo pass by using the special registration code GPFLASHEXPO1 — but only for the next 48 hours so you’d best hurry. At this point, that represents a $59 savings. Register here.
High-speed SerDes ports operating at multi-GHz speeds is one of the best connectivity tools in the system designer’s toolbox. You need some training to use this tool effectively and Keysight Technologies (the company formerly known as Agilent) is going to help you sharpen your SerDes saw with a free hour-long Webcast on September 25. The Webinar is titled “How to Optimize Your SerDes Design During the Pre-layout Phase” and it starts at 10am Pacific Time in the US.Read more...
By Adam Taylor
The demo for this will use CPU0 to communicate over the UART link to a laptop. We’ll send an 8-bit ASCII value from the laptop to the Zynq Soc’s UART. Once received, this 8-bit value will be transferred into the selected OCM memory address, which is shared between the two processors. Each time its private timer expires, CPU1 will read this memory address and set its GPIO output pins accordingly. LED’s on the MicroZed I/O Carrier Card connected to these Zynq SoC pins through the inter-board headers will display the received ASCII pattern. We’ll be able to visually confirm that the correct value has been passed between the CPUs from the display on the LED.
Here’s a neat trick I learned last week at X-fest in San Jose from Luc Langlois, Director of Global Technical Marketing and Digital Signal Processing at Avnet Electronics. The way to get FPGAs to perform direct conversion and processing on multi-GHz RF signals is to take the multi-GHz sample stream from the high-speed ADC and feed it into a polyphase channelizer to parallelize the processing.
You need math to understand this—math involving the equivalence theorem (heterodyne + baseband filter = bandpass filter + heterodyne) and the Noble Identity. Math that’s way beyond me so I’m not going to attempt an explanation here because I’ll just get it wrong.
However, I’m going to get the system-design part right, which is what you need to know after the math proves it’s OK for you to do it.Read more...
Did you miss the live Xilinx Webinar on Small Cell Backhaul Solutions? Nope, you didn’t because it’s on September 30. This free webinar discussed wireless backhaul capacity, networking, and signal processing challenges for small-cells. It then focuses on the technologies -- millimeter-wave (E and V bands) radio technology in particular, as well as hardware and software design solutions leveraging Xilinx All Programmable SoC platforms. Examples will be given showing how PHY and L2-L3 functions can be implemented in a flexible, low-risk, and cost-efficient manner.
For a quick overview of ways to add interactivity to digital signage with vision algorithms, take a look at “Practical Computer Vision Enables Digital Signage with Audience Perception,” a new article on the Society for Information Display’s Web site. The article discusses interactive vision algorithms including person discernment, face detection and analysis, and gesture recognition. This article is a joint project led by Brian Dipert from the Embedded Vision Alliance with Rabindra Guha and Tom Wilson from CogniVue, and Robert Green from Xilinx.
Pentek designs rugged, high-speed, real-time recording systems and embedded boards for DSP, SDR (software-defined radio), and data acquisition. The company introduced its Cobalt series of PCIe DSP boards based on Xilinx Virtex-6 FPGAs in 2009. When Xilinx 7 series FPGAs became available, Pentek added the Onyx board series to its product line. The Onyx boards are based on Virtex-7 FPGAs and they accept the analog and digital I/O boards originally designed for the Cobalt series.
Why tell you all of this? Because Pentek has developed multi-generational and multi-product-line perspectives with respect to FPGA-based product planning and development. Amazingly, the company just posted a 50-minute video, “Latest Design Strategies using Xilinx Virtex 7 FPGA for Software Radio,” on YouTube that walks you through the thought processes for developing such multi-generational product lines. Although the point of this video is using Pentek boards and Xilinx FPGAs for SDR, the first half of this video is filled with general design information and some great ideas that apply to most—if not all—products based on programmable logic.
Worth watching, even if SDR isn’t your thing.Read more...
Avnet has opened registration for the X-fest sites in Asia:
X-fest is a mix of product demonstrations and technical seminars. If you’re interested in learning about the use of Xilinx All Programmable FPGAs and Zynq SoCs, I can recommend these day-long events. I feel confident in telling you that it will be time well spent.
If you happen to be in Cannes next week for ECOC 2014, you’ll be able to see several 100Gbps demos built upon Xilinx UltraScale FPGAs sending and receiving data over multiple 25.78Gbps electrical connections:
You can see a video of that last demo right now. Click here.
Judges for the Elektra European Electronics Industry Awards 2014 just announced finalists in 16 product categories and have named the Xilinx UltraScale FPGA as a finalist in the Digital Semiconductor Product of the Year category.
Note: The UltraScale FPGA is the only programmable logic semiconductor device named as a finalist.
Last week at X-fest San Jose, I attended four technical sessions and the first was about memory interfaces and FPGAs—specifically Xilinx UltraScale FPGAs. The session had a lot of valuable general material about SDRAM in it. Bryan Fletcher, a Technical Marketing Director at Avnet, started by talking about the market dynamic between DDR3 and DDR4 SDRAM. DDR3 SDRAM is currently the volume leader, which means the cost/bit is lower for DDR3 memory than for other SDRAM generations.
That’s not going to last.Read more...
Join National Instruments (NI), Cloudium, and Xilinx as we tear open the Zynq-based NI VirtualBench All-in-One Benchtop Instrument (mixed-signal oscilloscope, function generator, logic analyzer, DMM, programmable dc power supply, and digital I/O control lines) and the Cloudium Systems Integrated Media Processing Platform (a cloud-centric, fanless, multimedia thin client). We’ll discuss how these products are designed and built—from an engineer’s perspective—during a mid-day Teardown Thursday session at ARM TechCon in Santa Clara, California. It’s all happening on Thursday, October 2nd starting at 11:30 am in the Main ARM TechCon Theater on the exhibit floor.
The NI VirtualBench All-in-One Benchtop Instrument
Haven’t registered for ARM TechCon yet? Better fix that now. Click here.
Yesterday, I published a blog about the Totem Virtual Reality headset, a Kickstarter project initiated by Vrvana. Totem uses a Xilinx 7 series FPGA for video processing, which involves 3D processing based on inputs from the headset’s HDMI input, a pair of stereo cameras, and an integrated accelerometer. It’s designed to work with:
The project funding level as of yesterday was just over $70,000. Today, it’s a Kickstarter Staff Pick and the pledge level has jumped above $100,000.Read more...
Vrvana’s Totem premium VR (Virtual Reality) headset plugs into an HDMI video source and plunges you into the world of 3D—and yes, the real-time video processing is done on a Xilinx 7 series FPGA. What makes the Totem headset merit the adjective “premium”? Could be the “no-compromise, full-HD-resolution 1080p OLED display” and the accompanying wide field of view. Could be the on-board stereo camera pair and the build-in accelerometer. Could be the immersive binaural sound generation that maintains the illusion of spatial reality. Could be all of those things plus a few more.