Would you like to brush up on SDN fundamentals? Let Gordon Brebner, a Distinguished Engineer at Xilinx, help. Gordon has been working on FPGA-based networking hardware for 25 years (!) and he’s got this stuff nailed. There’s nothing like training from someone who really knows the topic and Gordon compresses a lot of knowledge into a short, easily digested tutorial. Just click on his 30-minute video below.
Note: There are a very few audio gaps in this video and Gordon suggests you just imagine the words that are missing.
By Jack Ganssle, The Ganssle Group
I'm often asked what percentage of the engineering effort should be spent on architecture and design. It's probably not a meaningful question as different sorts of projects will have different answers. But NASA has studied this and for flight software, using the well-known and hardly-used COCOMO-II model, came up with this fascinating graph:
The little circles are "sweet spots" where the overall effort is minimized. Clearly, the bigger the application (in SLOC, or source lines of code), the more effort should go into up-front architecting and design. Of course, this information is hard to use since, at the outset of a development effort, it's hard to impossible to assess how many lines of code will be involved; the earliest time any size information is available is after architecting the system, so the graph is useful more as guestimation than as something for quantitative predictions. But it's useful, and unsurprising, to note that huge projects need more up-front work than tiny ones.
"Architecture" is usually poorly defined. That same document uses it in this fashion: "The software architecture of a program or computing system is the structure or structures of the system, which comprise software elements, the externally visible properties of those elements, and the relationships among them."
Note: This article originally appeared in Jack Ganssle’s free email engineering newsletter, “The Embedded Muse.” Although this article is about software, I am certain its content is 100% applicable to HDL-based design as well.
You can get a free subscription to “The Embedded Muse” with just your email address and you can read 17 years of back issues using that same link. No one makes learning about good engineering design as digestible and painless as Jack, as you can see from the above, concise article. I’ve read his newsletter for nearly two decades and consider it one of my “must reads” for my continued engineering education. In my opinion, Jack is a leading light when it comes to good, team-based engineering and the eradication of design bugs.
By Yuan Gu, Xilinx
You can implement several key wireless applications including radio and wireless backhaul very efficiently using Zynq SoC devices. Radio applications are especially good examples of this, where the Zynq SoC with both on-chip processor cores and programmable logic can implement fully-integrated hardware and software systems that handle all digital front-end processing. Every wireless application has different performance requirements and needs an appropriate OS.Read more...
Last week at NAB 2015, I stopped by the Barco Silex booth to see what was new. What I saw was this golden statue from the Academy of Television Arts & Sciences. It’s a Technology and Engineering Emmy Award for Barco-Silex’s work on the JPEG2000 video-compression standard.
The award recognizes Barco Silex and several other technology companies in the Video Services Forum (VSF) for their work on the advancement of interoperability for JPEG2000 video-compression systems. (See “Barco Silex accepts Technical Emmy at CES for JPEG2000 compression IP—Available for Xilinx All Programmable devices.”)
If you want to develop an FPGA Prototyping system that can handle any design size across multiple geographical locations, you’d better have big plans. That word—big—defines S2C’s just-announced Prodigy Complete Prototyping Platform, which consists of several existing components:
Many of these components existed before under the S2C name “TAI”. What’s really new is the plan to manage these large prototyping systems using a yet-to-be announced cloud-based application that can handle designs as large as 1 billion gates. S2C also plans to announce unprecedented debug capabilities that will allow for multi-FPGA, deep trace debugging.
Last week at NAB 2015, PathPartner demonstrated an ultra-low-latency hybrid HEVC/H.265 Video Decoder that optimizes performance by intelligently distributing the decoder’s task blocks between one of the on-chip ARM Cortex-A9 processors in the Zynq SoC’s Processor System (PS) and the on-chip programmable logic (PL) elements. The PS implements the HEVC Decoder’s parsing module and the PL executes computationally intensive task blocks. This distributed, hybrid decoder architecture is only possible because of the immense data bandwidth available between Zynq SoC’s PS and PL—thanks to the on-chip AXI interconnect fabric, which allows real-time transfer of the video-stream data back and forth between PS and PL.
Task-block allocation within the hybrid HEVC/H.265 decoder looks like this:
PathPartner Hybrid HEVC/H.265 Video Decoder task partitioning
The PathPartner HEVC/H.265 video decoder completely complies with Main Profile, level 4.1 HEVC ITU-T H.265 and ISO/IEC 23008-2 standards and can decode a 1080p30 video stream in real time on a Zynq Z-7045-2 SoC.
Avnet Electronics Marketing has just started to market a Xilinx Kintex UltraScale FPGA DSP Development Kit (Part Number AES-KCU-JESD-G) with high-speed JESD204B ADCs and DACs from Analog Devices. This kit combines the Xilinx KCU105 Eval Board based on a Kintex UltraScale KU040 FPGA with an Analog Devices AD-FMCDAQ2 data acquisition Eval Board, a full seat license for the Xilinx Vivado Design Suite: System Edition including System Generator for DSP and Vivado HLS, plus reference designs and docs. The Analog Devices AD-FMCDAQ2 data acquisition board incorporates a dual, 1Gsamples/sec, 14-bit, JESD204B AD9680 ADC and a quad, 2.8Gsamples/sec, 16-bit, JESD204B AD9144 DAC. Reference designs include an 8-lane, 12.5Gbytes/sec, JESD204B interface and an FFT-based channelizer.
Target applications for this kit include:
The advent of 4K video and the development of 12G-SDI, which can carry 4K video over one coax, is creating a niche for converters that can convert 12G-SDI into four 3G-SDI streams and Fidus showed me a small board based on a Xilinx Kintex-7 FPGA that does exactly that at last week’s NAB 2015. Here’s a photo of that board:
Just a day later at the show, Fidus came by the Xilinx booth showing the board packaged in a nice case:
Now there’s certainly a need for this converter, but there’s also a need for a converter that goes the other way—converting four 3G-SDI streams into one 12G-SDI stream—because many 4K cameras currently source video over four 3G-SDI ports. Minor board layout changes to swap in SerDes receivers for SerDes transmitter pairs on the 3G side and some FPGA reprogramming are all that’s needed (plus a different silkscreen for the case) because the design already has a 12G-SDI output, located in the upper left corner of the above image of the encased product. This ease in changing the product from one function to another is a hallmark of FPGA-based design.
Last week’s NAB 2015 show introduced me to a high-speed serial digital video interface, previously unknown to me, called V-By-One HS. I observed this interface in action at the inrevium/fidus booth where I saw a demo of a DisplayPort 1.2a to V-By-One transmitter and receiver implemented with two inrevium ACDC (Acquisition, Contribution, Distribution, and Consumption) 1.0 base boards based on Xilinx Kintex-7 FPGAs, a couple of V-By-One FMC cards, and inrevium’s V-By-One HS IP core. Here’s a photo of the setup at NAB 2015:
Got a heavy duty 8K or 4K video hardware project? Pressed for development time? Need to get to market before the competition? The inrevium/fidus team has a development platform for you. It’s called, quite simply, the 8K/4K Video Development Platform (formal part number TB-KU-060-ACDC8K) and it’s based on a Xilinx Kintex UltraScale KU060 All Programmable FPGA. There’s also 4Gbytes of DDR4 SDRAM on the board along with four SFP+ cages for optical modules and seven (!) FMC connectors of varying abilities.
Here’s a photo of the board shot last week at NAB 2015 in Las Vegas:
inrevium/fidus 8K/4K Development Platform for Xilinx Kintex UltraScale FPGARead more...
The inrevium/fidus booth was tucked way in the back of the North Hall of the Las Vegas Convention Center at NAB 2015 last week. It was packed with interesting development platforms for Xilinx All Programmable devices including this killer Artix-7 FPGA development platform called the ACDC 7. (The formal part number is TB-A7-200T-IMG.) This development product, like several more in the inrevium/fidus booth, is the result of an international collaboration between two Premier members of the Xilinx Alliance Program: inrevium, a division of Tokyo Electron Device Limited offering FPGA-based solutions for design teams, and high-end design house Fidus Systems. I’m going to devote several blog posts to these immensely interesting development boards, but this one’s about the ACDC 7 based on the Artix-7 FPGA.
Here’s a photo of the board shot last week at NAB 2015:
inrevium/fidus ACDC 7 Development Platform for Xilinx Artix-7 FPGA
By Adam Taylor
In the previous blog we introduced the Zynq SoC’s Gigabit Ethernet Controller, which provides Media Access Controller (MAC) capability. This is the first step in being able to establish an IP stack. Now we will look at how we can configure the MAC to send and receive packets using the example provided by Xilinx with the SDK, which demonstrates how the MAC works.Read more...
One of the most helpful things I saw for broadcast equipment developers this week at NAB 2015 was the OmniTek ULTRA 4K Video Tool Box, expressly designed to help you migrate your designs from HD to 4K video and from 3G-SDI to 12G-SDI digital video interfacing. The toolbox includes a multifaceted video generator, format converter, and analyzer. The toolbox generator can produce stills and video streams in all video standards from SD up to 4K from imported images, line patterns, zone plates, and combinations. The format converter provides automatic up/down/cross conversion between the full range of video input and output standards and includes multi-stream raster reconstruction for the various 4x3G (SQ & 2SI), 6G and 12G UHD video standards. The analyzer includes a multi-format picture viewer, physical layer analysis for SDI, status monitoring and error checking, gamut meters, CRC generation and checking, and video data analysis. The ULTRA 4K Tool Box hardware is based on a Xilinx Zynq Z-7045 SoC.Read more...
By Adam Taylor
So far on our Zynq development Journey of Discovery, we have yet to look at the Zynq SoC’s Gigabit Ethernet capabilites, which allow your application to be network enabled. Gigabit Ethernet provides very fast, flexible communications but Ethernet communications are a little more complicated than a simple RS-232 link. It’s nothing to be scared of, once you understand the topic and I think you will understand after the next few blog posts in this series.Read more...
A visit to the CoreEL Technologies booth at NAB 2015 was a real eye opener for me with respect to the number of available video codecs. The two back walls of the booth were dedicated to large-screen video demos of several FPGA-based video codecs running on a variety of Xilinx FPGA Eval Kits including:
In addition, CoreEL was showing an FPGA-based, packaged AV decoder module with integrated heat sink based on a low-end Xilinx Spartan-6 FPGA:
Because CoreEL’s video codecs are based on programmable FPGA technology, they’re highly configurable so they can be customized to meet specific requirements.
Last month, I-MOVIX announced its X10 UHD RF Ultra Motion super-slow-motion video camera system, which uses a wireless link between camera and processing unit to create a portable HD camera system that can shoot 3000 frames/sec at 720p or 2000 frames/sec at 1080i.
At NAB 2015 this week, I confirmed that the new UHD RF camera system employs Vision Research’s Phantom high-speed digital video cameras driving a super-slo-mo processing box based on Xilinx Virtex-6 FPGAs over a wireless link, shown as a belt pack in the above image.
Note: For more information about I-MOVIX UHD camera systems, see “FPGA-based i-movix X10 UHD Ultra Slow-Motion System accepts 1000fps in 4K, 2000fps in HD.”
You may think of an SFP cage as an I/O port for optical modules, since that’s how they’re generally used. Embrionix sees things differently. The company’s line of pluggable Video SFP modules use the SFP interface and form factor to create modular, configurable video and IP systems in a cost-efficient way. Members of the Embrionix Video SFP line include 12G-SDI, 6G-SDI, 3G-SDI, HD-SDI, and SD-SDI coaxial video interfaces and SDI-to-IP, HDMI, and composite converters. A key element contributing to the flexible nature of these video SFP modules is a Xilinx FPGA integrated directly into the module that performs both high-speed I/O conversion and video processing such as JPEG2000 compression and decompression in an extremely compact form factor.
Here’s a very short video demo shot at the Embrionix booth at this week’s NAB 2015 in Las Vegas. The demo shows I/O conversion from HDMI to SDI to SMPTE ST 2022 over Ethernet to SDI over fiber with some JPEG2000 compression thrown in, all performed by Embrionix IP.
The TICO Lightweight video compression scheme has a very important superpower: it can shoehorn a 12Gbps 4K video stream into a 10Gbps Ethernet port or even a 3Gbps 3G-SDI port with no perceptible loss in visual quality, making it possible to ship 4K video across existing, low-cost broadcast network infrastructure. This superpower makes it very easy for broadcasters to incorporate 4K video equipment into their existing network infrastructure. This week at NAB 2015, the IABM (International Association of Broadcasting Manufacturers) recognized the importance of TICO compression by presenting an IABM Game Changer Award to intoPIX for its TICO compression IP.Read more...
Here’s one of the really interesting demos at the Xilinx booth this week at NAB 2015. It’s a real-time HEVC H.265 I-frame video encoder from NGCodec, demonstrated by NGCodec’s CEO and co-founder Oliver Gunasekara. The short demo video below shows real-time encoding and also has a slick trick mode where you can see how the encoder is performing motion estimation in real time.
This demo is running on a Xilinx Kintex-7 FPGA. In the video, Gunasekara mentions that NGCodec is developing the full encoder for 4K video and targeting the bigger/better/faster/lower-power Kintex UltraScale FPGA.
Part of the vision for an IP-based broadcast video network involves the temporal synchronization of all network elements. This is especially important for live video with multiple feeds where all cameras and other video sources must synchronize to the same time. SMPTE ST 2022-6 High Bit Rate Media Transport over IP Network describes the encapsulation and de-encapsulation of video to and from IP networks using the Ethernet RTP (Real-Time Transport) protocol while SMPTE 2059-1 and -2 align the timing practices used in video production facilities with the IEEE 1588 PTP (Precision Time Protocol) standard. These standards are critical to realizing an all-IP broadcast video network.
In the following short video Antoine Hermans, CTO of Adeas, demonstrates SMPTE ST 2022 and 2059 IP cores running on Kintex-7 FPGAs aboard Xilinx KC705 Eval Kits. The live demo at this week’s NAB 2015 show in Las Vegas shows the two Xilinx eval kits synchronizing with a PC-based grand master to within about 10 pixels over the 10G Ethernet network.
Note: To see a vision of a future where all broadcast video runs over IP-based networks, see “IP-based Broadcast Video: A Vision from Thomas Edwards, VP of Engineering and Development at Fox Networks Engineering & Operations.”
Thomas Edwards has a vision for broadcast video in the year 2020. In that vision, he walks into the Fox Networks Broadcast Equipment Center and he sees no broadcast equipment. Instead, he sees a standard data center full of servers, Ethernet switches, and Ethernet cabling. Video travels over IP-based networks and video processing is virtualized. New cable channels appear with the swipe of a credit card.
Edwards is the VP of Engineering & Development for the Fox Networks Engineering and Operations Advanced Technology Group and his vision sits along the tracks running up ahead into the future. On those tracks is the Ethernet express train, which has been running along these tracks—faster and faster—for more than 30 years. During those three decades, Ethernet and IP-based networking have side-tracked nearly every other networking protocol in multiple markets as IP-based networking capabilities have expanded and gotten faster. Broadcast video, a very demanding application, is one of the few arenas yet to be converted but its time is at hand. In Edwards’ vision, broadcast video’s conversion to IP-based networking occurs over the next five years.
Here’s a very short video shot yesterday in the Xilinx booth at NAB 2015 where Edwards sketches out his vision:
As I write this, I’m eating a dry barbeque chicken sandwich at a table with six Chinese media moguls in the parking lot at the Las Vegas Convention Center (LVCC). I have no idea what my lunch companions are saying but that doesn’t matter because there’s a DJ playing Hip Hop music 20 feet away masking conversation in any language. I’m fortunate to be under a tent, which is shielding me from the blazing noon Nevada sun. You can feel the heat coming right through the fabric. The DJ switches to Lady Gaga while an executive from CBS broadcast distribution sits down in the chair next to me to enjoy a cheeseburger. Meanwhile, the Las Vegas Monorail rolls by, past the High Roller Observation Wheel—the Las Vegas interpretation of the London Eye. Welcome to NAB 2015—center of the universe for all things broadcast.
From the lunch tent at NAB 2015Read more...
The penalty for the Internet’s ability to ship packets anywhere on the planet (and off-planet) is overhead and one of the largest chunks of overhead is the TCP/IP stack. For most applications, we ignore the TCP/IP latency tax but for high-speed financial trading, where microseconds of delay translate into costs measured in millions of dollars, reducing TCP/IP overhead is worth a lot. The need to minimizeTCP/IP latency creates a niche for TCP/IP offload engines and FPGAs play a big role here. TCP Offload Engines (TOE) developed by the Dini Group and built from the configurable hardware on the Dini Group’s DNPCIe_40G_KU_LL PCIe board based on a Xilinx 20nm Kintex UltraScale KU040 FPGA have the ability to achieve the theoretical minimum Ethernet packet-processing latency at 10G and 40G Ethernet line rates. (See “DINI Group Announces Immediate Availability of Kintex UltraScale FPGA Board.”)
The following demo video, shot at the recent OFC 2015 conference in Los Angeles, shows a Dini Group DNPCIe_40G_KU_LL board running six Dini Group TOE128 TCP offload engines instantiated and running inside the board’s Kintex UltraScale KU040 FPGA.
Writing about functional safety in a blog post is like tiptoeing over quicksand. Functional safety is an incredibly deep subject that will suck you in at the slightest touch. There’s a brand new Xilinx White Paper (WP461) titled “Xilinx Reduces Risk and Increases Efficiency for IEC61508 and ISO26262 Certified Safety Applications” that can help you learn a lot about this complex subject in a mere 27 pages. The White Paper covers the key engineering attributes needed for a safe, dependable design and tells you how to use Xilinx technologies and design methodologies to solve the fundamental challenges relating to the design of safe systems. I found this White Paper to be clearly written and easily digested. It really should be your first step in learning about design for functional safety.
It’s really embarrassing for me to admit to how long it’s been since I designed a PCB. Suffice it to say that 1Gbps signals on a PCB were unheard of back then. Now, I’m writing about devices like the newest generation of Xilinx 16nm Virtex UltraScale+ devices with 40 to 128 GTY 32.75Gbps SerDes transceivers on chip. When I write about FPGA SerDes ports exceeding 10, 25, and 30Gbps in the Xcell Daily blog, I’m really dealing with transmission problems that are almost completely abstract in nature for me. The attenuation, reflection, and noise problems seem pretty big yet people clearly overcome these problems because actual products are already shipping and have been for years.
Perhaps you find yourself in a similar situation except that you actually need to get boards designed.
If so, consider visiting Stockholm this May. That’s SI Week where signal integrity guru Lee Ritchey will teach a 3-to-4-day class titled “Lee Ritchey: Very High Speed” that will cover the design of PCBs that handle fast differential signal pairs for everything from USB and PCIe to the fastest connections running at 32Gbps. The first three days of the class are theoretical. Day 4 involves practical matters. The class starts on May 18. Sign up here.
Ritchey will also be teaching a 1-day class titled “Lee Ritchey: Very High Speed” on May 22, also in Stockholm. Here’s a short class description:
“This one day course is intended to cover all of the technical issues involved in the design of very high speed differential pair signal paths. This is a thorough treatment of all of the topics that must be considered in order to be successful as the speeds of differential pair signal paths continue to increase.
28Gbps signaling is already being successfully shipped in high performance servers, routers and switches. When data rates exceed 5 Gbps there are a number of areas that need to be managed that were not significant issues at lower data rates. Among these are the type of glass weave used in laminates, the surface finish on the copper used for signal layers and the loss characteristics of the laminate itself. Effects of vias and other drilled holes can also have a significant effect on signal quality if not properly managed.
This course will draw upon more than 30 test PCBs built to determine the properties of new laminate systems as well as to measure the effects of vias, plane crossings and other features that might affect high speed signals.”
Note: Silica, which distributes Xilinx products throughout Europe, is one of the sponsors for these courses.
The ONetSwitch Kickstarter project, an open-source SDN platform based on a Xilinx Zynq SoC, just finished a successful funding campaign, passing its $50K funding goal just 24 hours before the end of the campaign. (See “An Open Source Kickstarter SDN project based on Zynq? For $649? Wowzers!”) The ONetSwitch platform is designed to allow you to write Linux software applications to achieve all sorts of network functions such as NAS, VPN, and Firewall. The Kickstarter campaign collected $53,769 in pledges from 119 backers. The project was undertaken by a company called MeshSr.
For more information there’s a:
Sumitomo Electric’s 4x25G QSFP28 LR4 optical module supports fiber links as long as 10km. This OFC 2015 video shows a Xilinx Virtex UltraScale FPGA driving one of these modules and 10km of optical fiber. The QSFP28 has the same footprint as a 40G QSFP+ optical module but it employs four 25Gbps lanes through an upgraded electrical interface. When compared to the alternatives, 100G QSFP28 increases density and decreases both power and price/bit, which is why it is fast becoming the universal form factor for data center optics.Read more...
Martin Gilpatric from Xilinx, who either cannot or will not make a bad video, takes all of 90 seconds in a video from OFC 2015 to fully explain the demo of a Virtex UltraScale FPGA on a VCU109 board driving a Finisar 100G ER4f CFP4 optical module connected to 50km of optical fiber—with no transmission errors. The ER4f spec includes a noise floor that requires the use of an RS-FEC to guarantee error-free transmission. The demo has a Xilinx 100G RS-FEC LogiCORE IP working in conjunction with the embedded, hard-core 100G Ethernet MAC in the Virtex UltraScale FPGA and, sure enough, the 50km link is running error-free.
This short, 90-second video from OFC 2015 shows a Xilinx Virtex UltraScale VU095 FPGA driving a 4x25G TE Connectivity QSFP28 SR4 4-channel optical transceiver connected to 100m of fiber. The remarkable thing about this transceiver is its low power consumption: 1.5W per end.
It’s hard to believe you can hear nearly half a dozen different high-speed I/O protocols named in a short 90-second video but OTN System Engineer Ian McBryan from Xilinx manages to name 2x100G OTN, OTL 4.4, a CFP4 optical module, Interlaken, and CAUI-4—all running on a 20nm Virtex UltraScale VU095 FPGA. What’s the point? The extreme, high-speed I/O programmability and flexibility of Virtex UltraScale devices.