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Kintex KU040.jpgYesterday, Xilinx announced that its 20nm Kintex UltraScale KU040 FPGA had moved to production status. This is the first Xilinx All Programmable 20nm device—indeed the industry’s first 20nm programmable logic device—to go into full production. The 20nm Kintex UltraScale KU040 FPGA incorporates 424,200 logic cells, 21.1Mbits of BRAM (Block RAM), 1920 DSP48E2 slices (see “The UltraScale DSP48E2: More DSP in every slice”), three PCIe Gen3/Gen4 hardened and integrated IP cores, 20 GTH 16Gbps SerDes transceivers, and 520 I/O pins.


Even though it’s the second smallest member of the Kintex UltraScale FPGA family, the 20nm Kintex UltraScale KU040 FPGA offers systems designers more on-chip resources than most of the members of the extremely successful Xilinx Kintex-7 FPGA family at significant power savings relative to the 7 series generation. The largest member of the Kintex UltraScale FPGA family, the KU115, offers roughly three times the number of on-chip resources: 1,160,880 logic cells; 75.9Mbits of BRAM; 5520 DSP slices; 6 PCIe IP blocks; and 64 GTH SerDes transceivers.


20-minute video explores the Zynq-based Red Pitaya Programmable Instrumentation Platform’s capabilities

by Xilinx Employee ‎12-18-2014 09:55 AM - edited ‎12-18-2014 09:56 AM (1,488 Views)

Martin Lorton, a video blogger in the UK, has just posted a practical, hands-on boot up and test video for the Red Pitaya, a Zynq-based, open-source, programmable instrument platform. Lorton’s video is nearly 20 minutes long and it just scratches the surface of this fascinating product. Lorton received the Red Pitaya from Red Pitaya’s European distributor, RS Components.


The first thing Lorton does is power up the board and measure the current draw from the USB power supply. It’s a low 800mA. He then tests out the Red Pitaya’s oscilloscope and signal generator functions. Lorton says he’s surprised with the oscilloscope application’s excellent, responsive display update rate. He also notes that the oscilloscope app supplied with Red Pitaya is rudimentary and that it’s possible to upgrade the performance through application programming.


In fact, you can create entirely new instruments by taking advantage of the on-board, dual-core ARM Cortex-A9 MPCore processor and the FPGA—both built into the Red Pitaya’s Zynq All Programmable SoC. One such instrument that’s been developed since the Red Pitaya’s introduction is an LCR meter, which seems to be of great interest to Lorton.


“OK... Here we go… Focus… Speed… I am speed.” – Lightning McQueen, “Cars”


Any system design today that’s moving a lot of data between chips, boards, or boxes needs speed—and lots of it—in the form of I/O bandwidth for:


  • Serial backplanes
  • Optical interfaces
  • Host and peer communication
  • Chip-to-chip communication


That’s the sole topic of a new Xilinx White Paper published today titled “Leveraging UltraScale FPGA Transceivers for High-Speed Serial I/O Connectivity” (WP458) by Brandon Jiao. This 24-page document tells you everything you need to know about high-speed digital communications using Xilinx 20nm UltraScale FPGAs.


For example, here’s a handy graphic that shows how many and what type of SerDes transceivers you get with each Virtex UltraScale and Kintex UltraScale family member:



UltraScale FPGA Transceiver Count.jpg



Here’s a similar graphic showing you the aggregate I/O bandwidth you get from the GTH and GTY transceivers on each of these devices:



UltraScale FPGA SerDes Aggregate Bandwidth.jpg



Finally, here’s a graphic comparing the aggregate device bandwidths available from 7 series and UltraScale Virtex and Kintex FPGAs:



UltraScale vs 7 series SerDes Aggregate Bandwidth.jpg



Does your design need 5.6Tbps or just 2Tbps?



If you’d like much more in-depth information on using these UltraScale SerDes transceivers, then download and read this new White Paper.




Keysight Webcast: Breakthrough Insight into DDR4/LPDDR4 Memory Greater than 2400Mbps

by Xilinx Employee ‎12-17-2014 11:05 AM - edited ‎12-17-2014 11:11 AM (347 Views)

Memory performance plays a major role in determining overall system performance; the actual bandwidth you eke out of DDR4 and DDR3 SDRAM is no exception. The Xilinx Vivado Design Suite includes the MIG (memory interface generator) that helps you create optimized memory controllers for your FPGA-based designs.


Our friends at Keysight Technologies have a 1-hour Webcast coming up on January 13, 2015. The Webcast title says it all: “Breakthrough Insight into DDR4/LPDDR4 Memory Greater than 2400 Mbps.” The Webinar is all about the latest test and measurement techniques needed for SDRAM running faster than 2400Mbps.


To quote Lord Kelvin, “If you cannot measure it, you cannot improve it.”


The Webinar presenter is Jennie Grosslight, Memory Test Product Manager at Keysight Technologies. I’ve met no one who knows more than Jennie about the ins, outs, and tricks of working with high-speed SDRAMs and I always learn something new every time I speak with her or listen to her presentations.


Register for the Keysight DDR4 Webinar here.



The Interlaken protocol provides chip-to-chip communications in many systems. The faster the communication, the better. Xilinx UltraScale FPGAs incorporate as many as 9 Interlaken integrated hard-core IP blocks to assist you in creating multi-chip systems that scream. The hard Interlaken cores handle data striping and de-striping across lanes, lane decommissioning, channel- and link-level flow control, and two levels of CRC. Each block supports Interlaken communications at a maximum total bandwidth of 150Gbps using 1 to 12 serial lanes operating at 6.25 to 12.5Gbps or 1 to 6 serial lanes operating at 12.5 to 25.78125Gbps. Of course, UltraScale devices have the high-speed serial transceivers needed to support these data rates.




4DSP PC820 PCIe Card.jpg



The PC820 PCIe card from 4DSP harnesses two FMC HPC connectors and an SFP+ optical transceiver socket to a Kintex UltraScale All Programmable device to create a design and implementation platform for applications as diverse as software defined radio (SDR), Radar/Sonar imaging, high-speed communications in data centers, and analog/digital signal processing. The FMC connectors allow you to add a variety of mezzanine cards that might carry ADCs, DACs, RF circuitry, or additional processing resources. 4DSP offers several such FMC mezzanine cards. Here’s a block diagram of the card:



4DSP PC820 Block Diagram.jpg



Note: This is the second PCIe card based on a Xilinx Kintex UltraScale card announced and covered in Xcell Daily today. I sense a trend here.


DINI Group Announces Immediate Availability of Kintex UltraScale FPGA Board

by Xilinx Employee ‎12-16-2014 02:34 PM - edited ‎12-16-2014 03:04 PM (543 Views)

According to this press release appearing on, DINI Group has just announced that its DNPCIE_40G_KU_LL PCIe FPGA board based on Xilinx Kintex UltraScale All Programmable devices is now available. (The other DINI Group designation for this board is “Daughter of Godzilla's Bad Hair Day,” in keeping with the company’s unique product naming system.) The board can be populated with a Kintex UltraScale KU070, KU060, KU040, or KU035 device in an 1156-pin, flip-chip BGA package.






The new board also features a QFSP+ optical transceiver socket, two SFP+ optical transceiver sockets, 4Gbytes of on-board DDR4 SDRAM, 144Mbytes of low-latency RLDRAM3, a GPS input for precise time stamping (for high-speed, low-latency packet-processing applications), and “enough debug LEDs to illuminate a small Koi pond.” Here’s a block diagram of the board:


DINI Group DNPCIE_40G_KU_LL block diagram.jpg




The 2014.4 release of the Vivado Design Suite is now available. There are a few reasons for you to consider upgrading. Among the several new features, the latest version of the Vivado Design Suite supports the -1L and -2L industrial, low-power speed grades for Kintex-7, Artix-7, and Zynq All Programmable devices. You’ll also find enhanced support for partial reconfiguration for both 7 series and UltraScale devices. (See “Partial Reconfiguration in Xilinx UltraScale devices allows you to dynamically reconfigure nearly everything on the chip.”)


Download the new 2014.4 version of the Vivado Design Suite here.

Is FPGA configuration security for intellectual property an issue in your application?


Say “Yes.”


Want more information on using the Vivado Design Suite tools to encrypt configuration bit streams for better IP protection? Watch this Xilinx Quick Take video:





Partial Reconfiguration gives you a way to reuse resources on an FPGA based on changing system needs. Like prior generations of Xilinx All Programmable parts, UltraScale devices allow partial reconfiguration of logic elements including CLBs, BRAMs, and DSP slices. UltraScale devices also allow you to dynamically reconfigure clock-management blocks (the MMCM and PLL), clock buffers, Gigabit transceivers, and other I/O resources.


The latest Vivado Design Suite tools provide floorplanning and DRC tools to put Partial Configuration in your hands for both UltraScale and 7 series All Programmable devices including the Zynq SoC. UltraScale devices also provide Partial Reconfiguration with finer granularity than previous All Programmable device generations. There’s also a brilliant new IP block, a partial-reconfiguration controller, available through Vivado to help you better use these features in your application.


Christoph Fritsch from Xilinx presented a 15-minute talk with details on designing Industry 4.0 Cyber-Physical Systems at the SPS IPC Drives show in Nuremberg, Germany last month. Embedded Know-How, an online incarnation of Embedded Control Europe magazine, recorded the presentation. You can watch it here.


Fritsch made several important points about Industry 4.0 in this talk. Key underlying elements include:


  • Green power—for lower operating expenses (OPEX)
  • Context-Aware Intelligent Systems—Sensor-based systems that include advanced sensing abilities such as specialized vision to help automate complex industrial processes
  • The Industrial Internet of Things—the convergence of dozens of mutually incompatible, legacy industrial networks into a universal, industrialized version of Ethernet
  • Functional safety—to meet new governmental safety requirements such as IEC61508


It should not be surprising to learn that Xilinx and several of its Alliance Program members are actively working in all of these areas. For example, the Xcell Daily blog just discussed the Green Power work being done with QDESYS to develop advanced motor controllers based on Xilinx Zynq All Programmable SoCs and SiC (silicon-carbide) switching power transistors (see “10KW power inverter and motor controller employs SiC MOSFETs under Zynq control).


Again, to see the 15-minute video, click here.

Lighthouse Imaging develops and manufactures endoscopic visualization systems and provides optical imaging solutions for the medical device industry. Today, an article on the Design & Reuse Web site said that Lighthouse Imaging is using the Zynq-based PLDA SoMZ-7045 System on Module as a fast way to create commercial products. “Our image acquisition and processing capabilities, as well as overall design time, have been greatly bolstered by the availability, compactness, and feature set of the PLDA SoMZ platform,” said Benjamin Gray, Director of Research and Development at Lighthouse. “PLDA has allowed us to convert client wish lists to commercial products in record time.”



PLDA SoMZ-7045.jpg



For more information on the PLDA SoMZ-7045 System on Module, see “Ultra-Compact System on Module based on the Zynq Z-7045 SoC is only 3 inches wide.”



12 more companies join NBASE-T alliance for 2.5 and 5Gbps Ethernet standards

by Xilinx Employee ‎12-15-2014 10:21 AM - edited ‎12-15-2014 10:21 AM (386 Views)

NBASE-T Logo.jpgThe NBASE-T Alliance, an industry-wide cooperative effort to promote the development of 2.5 and 5 Gigabit Ethernet over twisted pair copper cabling (2.5GBASE-T and 5GBASE-T) now has 12 new members:


  • Aruba Networks
  • Brocade
  • Cavium
  • Centec Networks
  • CME Consulting
  • Intel
  • Microsemi
  • Qualcomm
  • Ruckus Wireless
  • Shenzhen GLGNET Electronics Co., LTD.
  • Tehuti Networks
  • Vitesse Semiconductor


Xilinx is already a member of the NBASE-T alliance. For more information about the development of the 2.5 and 5Gbps Ethernet standards, see:


NBASE-T aims to boost data center bandwidth and throughput by 5x with existing Cat 5e/6 cable infrastructure



For additional information about the PHY technology behind NBASE-T, see


Boost data center bandwidth by 5x over Cat 5e and 6 cabling. Ask your doctor if Aquantia’s AQrate is right for you



By Adam Taylor


This week’s blog is going to again look at the Zynq SoC’s XADC. A MicroZed Chronicles reader posed a very interesting question last week and I think that it is important to address this aspect of the XADC. It’s important enough to interrupt the ongoing discussion of the use of the PicoBlaze processor in the Zynq, which we’ll return to after this interlude.


Dave Jones does a video review of the Digilent Analog Discovery, which is based on a Spartan-6 FPGA

by Xilinx Employee ‎12-12-2014 03:33 PM - edited ‎12-13-2014 11:03 PM (823 Views)

Dave Jones just posted a 53-minute video review (!) of the Digilent Analog Discovery multi-function instrument, which combines:



  • 2-Channel Oscilloscope
  • 2-Channel Waveform Generator
  • 16-Channel Logic Analyzer
  • 16-Channel Digital Pattern Generator
  • ±5VDC Power Supplies (50mA per channel)
  • Spectrum Analyzer
  • Network Analyzer with Bode, Nichols and Nyquist plots



This is a USB instrument. The digital functions and control are implemented with a Xilinx Spartan-6 FPGA and the two 14-bit analog channels are implemented with an Analog Devices AD9648-125 2-channel, 125Msamples/sec ADC. The instrument sells for $237, which is a bargain (currently on sale for 15% off for the holidays!). However, the academic pricing is $158 and the student price is an amazing $99.


As usual, Dave packs the review with plenty of insights that every engineer should hear. Here’s the review:


If you’re looking at designing a next-generation wireless basestation, you’re looking at developing a lot of new technology including adaptive antenna array (AAA) systems and CRANs (cloud radio access networks). The way data moves and how it is processed in these next-generation basestations will change like never before. Xilinx has published a new 56-page White Paper titled “The Application of FPGAs for Wireless Base-Station Connectivity”(WP450) to help you. Check it out.



Next-Generation CRAN Basestation.jpg

Analog Devices has just announced an integrated direct conversion receiver development platform for radar systems—the $650 AD-FMCOMMS6-EBZ—which is a 400MHz to 4.4GHz receiver (1350 MHz to 1650 MHz with installed filters) supporting the L and S radar bands. The platform’s VITA57-compliant form factor ensures seamless connectivity to FMC (FPGA mezzanine card) platforms including the Zynq-based ZC702 and ZC706 Evaluation Kits. The AD-FMCOMMS6-EBZ is suitable for defense, communications, and instrumentation radar systems requiring high performance and a compact footprint in applications such as early warning detection, weather surveillance, and air-traffic control systems.



Analog Devices AD-FMCOMMS6-EBZ platform.jpg



The AD-FMCOMMS6-EBZ employs an I/Q demodulator that implements direct or zero-IF conversion. By contrast, super-heterodyne receivers must perform several frequency translations so single-frequency I/Q demodulation increases system performance and reduces power consumption by reducing both receiver complexity and the number of required conversion stages. The architecture avoids image-rejection issues and unwanted mixing by adding an amplification stage that maintains full-scale input to the A/D converter. In addition, the image rejection inherent in I/Q demodulation removes the need for an expensive anti-aliasing filter. The AD-FMCOMMS6-EBZ platform’s on-board local oscillator and converter clock share the same reference signal to prevent smearing.


Analog Devices has created suitable Quick Start configuration files for the ZC702 and ZC706 Evaluation Kits, available here as a downloadable SD Card image.

10KW power inverter and motor controller employs SiC MOSFETs under Zynq control

by Xilinx Employee ‎12-11-2014 03:55 PM - edited ‎12-12-2014 10:58 AM (712 Views)

Multilevel power converters employ more than two voltage levels to achieve smoother and less distorted ac-to-dc, dc-to-ac, and dc-to-dc power conversion and motor control. QDESYS has developed a laptop-sized, 10KW, 3-level power inverter and motoro controller based on twelve SiC (silicon-carbide) MOSFETs. The design employs a Zynq-based Avnet MicroZed or PicoZed SOM (System on Module) to control the SiC power MOSFETs using RPFM (regenerative pulse frequency modulation) and to provide system communications with the outside world. (For more technical information about RPFM, see Dr. Giulio Corradi’s EDN article “FPGA high efficiency, low noise pulse frequency space vector modulation--Part I” and “FPGA high efficiency, low noise pulse frequency vector modulation—Part II.” PDFs of these two articles are attached below.)


Here’s a block diagram of the QDESYS design:



Qdesys 3-Level Power Inverter.jpg



Here’s a photo of the resulting system including the QDESYS power-inverter carrier card, the Avnet MicroZed SOM, and an ISM Networking FMC Module.



Qdesys 3-Level Power Inverter Board Photo.jpg


SiC MOSFETs can switch higher voltages and currents at higher temperatures (175°C), have a larger band-gap and high voltage breakdown (1200V), and exhibit fast switching capabilities that can deliver better performance for power inverters when compared to IGBTs. The 3-level power inverter design mitigates motor-control issues caused by long power cables between the controller and the motor or load by employing smaller voltage steps. The smaller voltage steps also reduce voltage surges and curb rise times at the motor terminals. The waveform output is cleaner because the effective switching frequency of a 3-level power inverter is twice the actual switching frequency. Here’s a comparison of the two waveforms for illustration:



2-level versus 3-level power inverter waveforms.jpg



For more information about the QDESYS SiC power inverter and motor controller, click here. For a complete presentation about this technology, click here.



The Xilinx Zynq SoC is one powerful embedded processor with its dual-core ARM Cortex-A9 MPCore processor and a big chunk of FPGA for heavy-duty processing tasks. But let’s say you need even more microprocessor horsepower than you can get from a dual-core ARM Cortex-A9 processor. Let’s say you want a quad-core device because your design needs to breathe ARM-scented dragon fire. You can’t get a quad-core Zynq SoC today but you can get the SBC4661 from Micro/sys. It’s based on a Freescale quad-core i.MX6 multimedia CPU connected to a Xilinx Kintex-7 FPGA (70T, 160T, 325T, or 410T) using PCIe and a fast memory-bus interface. The Kintex-7 FPGA gets access to the outside world through 200 I/O lines and 12 differential analog inputs. Here’s a block diagram of the board:



Micro-sys SBC4661 Block Diagram.jpg



Micro/sys SBC4661 single-board computer block diagram



The Freescale i.MX6 device provides a 1GHz quad-core ARM Cortex-A9 MPCore processor and the on-board Kintex-7 FPGA provides 65,600 to 406,720 logic cells and 240 to 1540 DSP slices depending on which Kintex-7 device you order on the board. That amount of programmable logic is comparable to the amount available on the Zynq SoCs that incorporate programmable logic based on the Kintex-7 logic cell design (Z-7030, Z-7035, Z-7045, and Z-7100), although the Zynq Z-7100 actually gives you far more DSP resources—about 30% more.


Keep in mind that there are at least four significant differences with the SBC approach besides the DSP gap. First, the Micro/sys SBC4661 is a board-level product and not an IC, so it’s physically a lot larger. The SBC4661 measures 4.5 inches by 6.5 inches. Second, you’re not going to be able to take advantage of the incredible bandwidth between the Zynq SoC’s PS (processor system) and PL (programmable logic), which is a result of the thousands of programmable I/O lines in the on-chip AMBA AXI4 interconnect fabric that connects the PS and PL together. You’ll need to perform some system-level simulations to see if that performance difference is going to be important in your system design. Third, you’re not going to see the same high level of integrated tool support that you get for the Xilinx Zynq SoC’s PS and PL from the Vivado Design Suite. Finally, if you need more than the SBC4661’s 200 I/O lines, you can get those with one of the larger Zynq devices.




FPGAs are great prototyping targets for developing new IP blocks, algorithms, and entire ASICs. S2C has just announced its latest prototyping platform, the SingleE V7 Logic Module based on a Xilinx Virtex-7 2000T 3D FPGA. It measures a diminutive 260mm x 170mm and features:


  • 960 I/Os on 8 high-speed connectors
  • Access to a library of over 70 daughter cards for quickly building a prototype target
  • On-board DDR3 SO-DIMM socket extending to 8Gbytes of memory running at 1600Mbytes/sec
  • Remote control management through Ethernet and USB for programmable clock generations, design resets, virtual I/Os and switches, I/O voltage setting, and monitoring of voltage/current/temperature and hardware status
  • Multiple SingleE V7 Logic Module management from one PC


S2C SingleE V7 Logic Module Block Diagram.jpg



The S2C SingleE V7 Logic Module can take on many hardware development tasks including:


  • Running ESL simulations to evaluate model accuracy
  • Validate SoC software on a target architecture
  • Algorithm development using real hardware
  • Create corner test cases in software and run exercises on a hardware prototype
  • Run regression tests on FPGA prototype hardware using vectors stored in the host computer



OKI IDS and Xylon team up to address the ADAS market in Japan

by Xilinx Employee ‎12-11-2014 09:33 AM - edited ‎12-11-2014 09:34 AM (421 Views)

Two Xilinx Premier Alliance Members, OKI IDS and Xylon, have partnered to tackle Japan’s ADAS (Advanced Driver Assistance Systems) market. Xylon’s logicBRICKS IP Cores Library includes numerous graphics and video-processing IP blocks optimized for Xilinx All Programmable devices and has an outstanding record of ADAS design wins in Europe and North America. OKI IDS is an OKI Group company specializing in IP and design services for FPGA-based designs in Japan. This agreement will facilitate access to Xylon’s logicBRICKS technologies in the growing Japanese ADAS market and will significantly shorten the design and development cycles for ADAS projects undertaken by OKI IDS.


As an example of what Xylon logicBRICKS can do, here’s a recent 40-second video of a Zynq-based Xylon demo at the Vision Expo in Stuttgart showing real-time fusion of visible and thermal IR video streams to create a live, multispectral video display:





The Hybrid Memory Cube Consortium (HMCC) rolled out the HMCC 2.0 interface specification for the Hybrid Memory Cube late last month. Notably, HMCC 2.0 raises the maximum per-lane data rate from 15 to 30Gbps. That makes it a good time to point out that the Xilinx Virtex UltraScale VU095 FPGA that started to ship to customers last May has 32 on-chip GTY transceivers capable of 32.75Gbps operation. Xilinx demonstrated HMC compatibility at SC14 in New Orleans last month using the Open-Silicon HMC controller IP. (See “Want to see the Micron HMC (Hybrid Memory Cube) transfer 40+Gbytes/sec? Watch the demo video from SC14.”) There appears to be no major obstacle in scaling this IP to meet the new HMC 2.0 spec.


Here’s the video of the HMC demo at SC14, in case you missed it.



XAPP1220, “UltraScale FPGA BPI Configuration and Flash Programming” by Stephanie Tapp and Ryan Rumsey, tells you how to use parallel x16 NOR Flash memory connected to a Xilinx Virtex UltraScale FPGA’s master byte peripheral interface (BPI) to get blazing-fast device configuration. How fast? Well, how about 199.13msec for reading all 286,746,912 configuration bits into a Xilinx Virtex UltraScale VU095 device? That’s the result obtained when running the NOR Flash memory’s clock at 90MHz. (The Virtex UltraScale FPGA’s maximum rate on the BPI port is actually 111MHz). Flash programming times are also comparatively quick using the FPGA’s JTAG port to send the programming data to the BPI-attached NOR Flash through the FPGA. Here’s a diagram of the connection between the FPGA and a Micron NOR Flash memory:



UltraScale FPGA to NOR Flash Connection Diagram.jpg



XAPP1220 explains how to program the Flash memory using the Xilinx Vivado Design Suite tools. The Micron NOR Flash memory starts in asynchronous read mode by default. XAPP1220 walks you through the steps needed to prepare a NOR Flash programming file using Vivado tools so that the resulting bitstream configures the NOR Flash memory for synchronous burst-mode transfers. Note that if you don’t configure the Flash memory for burst mode transfers, then you lose more than 90% of the technique’s performance. This technique works for all Xilinx FPGAs based on the UltraScale architecture. You should note that Xilinx 7 series FPGAs also have BPI ports that can deliver fast configuration times, as described in XAPP587, BPI Fast Configuration and iMPACT Flash Programming with 7 Series FPGAs.


Two additional items of note:


  1. XAPP1220 discusses this technique using the Vivado Design Suite while XAPP587 employs the Xilinx ISE Design Suite.
  2. XAPP1220 discusses this technique for using Vivado to configure the Flash memory for Xilinx UltraScale All Programmable devices but it applies equally well to 7 series devices.






As Bullwinkle J Moose would say, “Nothing up my sleeves. Presto!”


The new video below shows you how easy it is to create, compile, and run a new program for the Xilinx Zynq SoC. If you need an application processor with better reaction times to real-time events, then the Zynq SoC is a strong candidate.




ARRI ALEXA 65 Promo.jpg



Last night at the Linwood Dunn Theatre in Hollywood where Oscar candidates are screened by The Academy of Motion Picture Arts and Sciences each year, filmmakers and cinematographers had the opportunity to try out the new FPGA-based ARRI ALEXA 65 6.5K digital cinecam I blogged about yesterday. (See “ARRI’s ALEXA 65—a 65mm, 6.5K pro digital cinecam—reaches its market in less than a year thanks to FPGAs.”)



ARRI ALEXA 65 Event at the Linwood Dunn Theatre.jpg



Although ARRI’s ALEXA 65 employs Xilinx Kintex-7, Artix-7, and Spartan-6 FPGAs for various internal functions including image-processing, signal conditioning, and image-sensor control, last night’s gala event gives me the opportunity to discuss two non-FPGA-related topics connected to ARRI’s new top-of-the-line camera system.


Item one: The larger format of the ALEXA 65 digital cinecam requires a new set of lenses to focus the action taking place in front of the camera on the significantly larger imaging area of the ALEXA 65’s 65mm CMOS sensor. ARRI has adapted the world-renown Hasselblad still-camera lenses for cinematography by re-housing them in cine-class lens barrels co-developed with IB/E Optics and by equipping them with ARRI’s LDS (Lens Data System), which reports frame-accurate metadata to the camera on the lens’ focus, iris, and zoom settings. The camera records that metadata with each captured image frame.



ARRI Hasselblad Lenses for ALEXA 65 Digital Cinecam.jpg




Item two: Yesterday, I listed a number feature films and television shows shot with ARRI’s FPGA-based ALEXA camera systems. Today, I discovered an extensive list of such films (437 titles!). In particular, I learned that one specific film was shot with an ALEXA camera system— last summer’s sleeper hit, “Guardians of the Galaxy”—which gives me an extremely flimsy excuse for posting the movie trailer for that film in Xcell Daily.


It’s been a year since I wrote about the advantages inherent in the Xilinx UltraScale architecture and the improvements made in the Vivado Design Suite tools that result in high device-utilization rates with high post-route Fmax performance and reduced power consumption. (See “What’s the Right Road to ASIC-Class Status for FPGAs?”)


There are multiple advantages to be realized here:

  • High utilization means you can fit even larger designs into large UltraScale devices or you can fit smaller designs into smaller, more cost-effective devices.


  • High post-route Fmax means that you do not trade off performance for utilization. You get both high utilization and consistently high performance from the Xilinx UltraScale devices and you can use more cost-effective speed grades.


  • Lower power consumption—well that doesn’t really need an explanation, does it? Lower power consumption reduces manufacturing costs by reducing cooling and power supply requirements.




ARRI Group, the world’s largest supplier of motion picture equipment, rolled out its ALEXA 65—a 65mm (54.12 x 25.58 mm), 6.5K digital cinecam—back in late September at the cinec event in Munich. The camera is now available through ARRI Rental. The heart of the ALEXA 65 is ARRI’s immense A3X CMOS image sensor with 6560 x 3102 photosites. That’s 3x larger than the 2K Super 35 CMOS imaging sensor in the company’s ALEXA XT digital cinecam. In addition, the ARRI A3X CMOS image sensor boasts better than 14 stops of DR (dynamic range). Both image sensors are ARRI proprietary designs. The ALEXA 65 bristles with Xilinx FPGAs, which gave ARRI a remarkably short time to market (less than one year from getting the green light to start the design in January, 2014 to introduction in September) and all of the risk reduction and flexibility the company wanted for future product upgrades including a planned upgrade to 27fps open-gate operation scheduled for January.


Avnet’s latest online issue of AXIOM, a news and features magazine for the engineering community, contains an article on the use of Zynq-based SOMs (Systems on Modules) for developing real-world products. The article, titled “Avnet Zynq SoMs Decrease Customer Development Times and Costs,” describes two companies that have successfully developed products with Avnet’s Zynq-based MicroZed SOM. The first example is the SmartDAQ 1000 ISP (Intelligent Sensor Platform) from Mountain Storm Instruments (MSI) in Los Alamos, NM. Here’s a photo of the SmartDAQ 1000 ISP:



Mountain Storm Instruments SmartDAQ 1000 ISP.jpg



The red pcb at the bottom left of the image is the Avnet MicroZed SOM. It’s plugged into the MSI sensor board using the two high-density I/O connectors located on the bottom of the MicroZed card. MSI’s founder John Battles explains why he chose the Avnet MicroZed SOM: “MicroZed has been designed for OEM use in real products. For small start-ups, order size flexibility is essential when the market demand is unknown.”


Ajile Light Industries develops high-speed, high-definition image sensor and DMD display designs for applications in industrial inspection, 3D metrology and medical devices. To ease the task of developing Zynq-based systems for these applications, the company created a development system designed to simplify the integration and management of light projectors and cameras. The Ajile System is also based on an Avnet MicroZed SOM. Here’s a block diagram of the system:



Ajile System Block Diagram.jpg



Jeremy Gribben, Ajile’s Chief Technology Officer, says that the Avnet MicroZed “improves the development time of a company our size. The training, tutorials and reference designs provided by Avnet were helpful to get us up and running. The support documentation is at a higher level than other similar solutions.”


Avnet now offers two SOMs: the MicroZed and the PicoZed, and associated I/O carrier cards.

By Adam Taylor



Having previously introduced the concept of driving a CCD to demonstrate the deterministic nature of the PicoBlaze and the ease with which we can re-program the PicoBlaze using the Zynq PS (processor system), I thought in this blog I should show how we can create our first waveforms in accordance with the CCD datasheet.


Although we have two PicoBlaze processors within this design, this example only needs one of them because there are only four image and four register clocks and one PicoBlaze processor will suffice. When things get more complex, we’ll need the additional PicoBlaze processor.

We will be using a software-based counter to generate the waveforms. The software will update a register value each time the counter expires and will then output the content of this register to create the waveform we require for the image and register clocks.


Based on the data sheet, the e2v CCD 230-42 image clocks are driven with a typical timing of 144 microseconds for each line. The software must read out each line via the output register with a typical timing of 1333ns. The image clocks are therefore broken down into a nine 16μs time slots. That means we should configure the counter delay for 16μs and manipulate the register as necessary once the timer elapses. We use a different value to create the register clocks.


The PicoBlaze processor in this design is clocked at 40MHz (although we could do 150MHz easily in the Xilinx Zynq SoC). The clock cycle is therefore 25nsec and the PicoBlaze always takes two clock cycles per instruction. Therefore the image clocks will need the delay loop to count down from 64 or 0x40. Now how did I get that number? Like this:



16μs / 25ns = 640


640 / 2 = 320 –> takes into account the two clock cycles per instruction


320 / 5 = 64 –> accounts for a 5-instruction delay loop



At the end of each loop, the software will manipulate the output register to create the desired waveform, which is constructed by using OR and AND operations to set and clear specific bits within the predefined register.


Assuming we’re using an 8-bit register (initialized to 0x00), we can OR a constant with the appropriate bit set with the existing value of the register to set a bit in the register. Using the OR command leaves other bits unchanged.


To clear a bit we use the AND function. Again this is similar to the OR function however we need to use a mask of all ‘1’s except for the bit we want to clear. Both these logical operators are needed to ensure that we do not change other bits within the register.


Using this approach, we can easily recreate the required digital waveform as shown below. Should we want to adjust these timings, we need only change the PicoBlaze software. Depending upon the clock used in the PL, we can have very fine timing precision using this technique.






Once we have output the image line clocks, we must also output the register clocks that move each pixel in that line through the CCD’s output amplifier. This can be achieved using a code loop that executes for the required number of pixels on the line. In the simplest readout structure, we clock out all the pixels in the in a line.






We can make alternations and optimizations to these timings easily using the PS interface to change the waveforms.


The simple PSM program file I used to create this example is available on the Github repository


Next week I will look at an interesting XADC question that was asked about a previous MicroZed Chronicles blog post.





Please see the previous entries in this MicroZed series by Adam Taylor:


Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD


Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4


Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3


Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two


Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze


Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC


Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC


Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP


Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!


Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP


Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)


Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications


Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)


Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC


Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores


Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS


Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts 


Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4


Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3


Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two


Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One


Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts


Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8


Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7


Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6


Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5


Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC


Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays


Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays


 Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card


Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29


The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28  


The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27


The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26


The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25


The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24


The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23


The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22


The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21


Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20


Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19


Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18


Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17


The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16


Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15


MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14


More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13


MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12


Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11


Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10


Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9


MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8


Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7


A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6 


Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5


Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4


Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3


Adam Taylor’s MicroZed Chronicles: Setting the SW Scene


Bringing up the Avnet MicroZed with Vivado






Saleae Logic Analyzer.jpgSparkfun started selling the 500Msamples/sec Saleae Logic Pro 8 logic analyzer today for $399. Each of the Logic Pro 8’s eight multi-use inputs can serve as a digital input at the full sample rate or as a 10-bit, 50Msamples/sec analog input with a 1MHz input bandwidth. The analyzer’s digital input range is 1.2 to 5.5V and the analog input range is 0 to 5V. This thing is tiny! It measures just over two inches (53mm) on a side and is less than half an inch (12mm) thick. “Gotta be an FPGA in there,” I thought.



There is.



Fortunately, Saleae is very proud of the design and craftsmanship that went into the development of the Logic Pro 8 and the company’s Web site carries this image:




Saleae Logic Analyzer with Spartan-6 FPGA.jpg



That’s a Xilinx Spartan-6 LX16 FPGA prominently featured on the circuit board. This Spartan-6 FPGA incorporates 14,579 logic cells, 576Kbits of block RAM, and 32 DSP48A1 DSP slices—so it provides a lot of raw processing power to the instrument. (Click here to see the video.)


The logic cells and memory have obvious use in this application but what does Saleae need the DSP for? According to the Saleae Web site, “The FPGA also has the capability of performing over 5 billion DSP operations per second (over 10 billion on Pro 16). When you use more analog channels than can be streamed over USB at once, we need to filter and decimate that data in the FPGA – reducing the bandwidth without introducing aliasing. Logic Pro 16 produces analog data at a rate of 9.6Gbit – that’s a lot of data to process in real time!” (Yes, there’s a 16-channel version of the analyzer available as well. It has the same input specs but twice as many channels for an additional $100.)


(Note: The other large chip appearing on the board is a Cypress CY7C68013A High-Speed USB Peripheral Controller, which provides the Saleae Logic Pro 8 logic analyzer with its USB host connection.)

About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.