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Xilinx User Community Forums :
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Old ISE Board -- no new thread :
Re: Synthesis Help
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Synthesis Help
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saed_swedan80
Visitor
Posts: 4
Registered: 09-23-2007
Message 1 of 7
Viewed 5,527 times
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Hi,
i'm using ISE 9.2i and Vertex 5. I'm Implementing a multiple squaring algorithms in ISE and wish to compare their performance with each other. Here is what i get when i synthesize on of the algorithms:
"Minimum period: 4.083ns (Maximum Frequency: 244.912MHz)
Minimum input arrival time before clock: 3.180ns
Maximum output required time after clock: 2.570ns
Maximum combinational path delay: No path found"
the problem is with the "Maximum combinational path delay: No path found".
my questions are:
Is this normal, or is there something wrong that needs to be corrected?
what exactly does "Minimum period" measure, (i.e. can i use it to set the device clock frequancy), and can i use it as a performance measure?
what exactly does "Maximum pin delay" measure, and can i use it as a performance measure?
can someone please reply asap, i need this for my master's thesis.
Thanks in advance...
p.s.: if you need the code for the algorithm, i'll be happy to provide it, but please help me :).
Regards,
Saed Swedan
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09-23-2007 01:06 AM
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Re: Synthesis Help
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gszakacs
Expert Contributor
Posts: 1026
Registered: 08-14-2007
Message 2 of 7
Viewed 5,510 times
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the problem is with the "Maximum combinational path delay: No path found".
my questions are:
Is this normal, or is there something wrong that needs to be corrected?
This is normal if there is no path from a top-level input to a
top-level output that is not clocked. I assume your design is
fully pipelined, thus no combinatorial paths from input to output?
what
exactly does "Minimum period" measure, (i.e. can i use it to set the
device clock frequancy), and can i use it as a performance measure?
"Minimum period" after synthesis is an estimate of the clock period for
signals inside the design. Thus you can invert this to get a feel
for maximum clock frequency. This is not a hard actual number, as
you can only see the true numbers after place&route. Also
this may not be the actual minimum period for the design if you are
limited by input and output timing. It only calculates the worst
case path timing from clock edge to clock edge for flip-flops within
the design. So if you have a path consisting of external input to
flip-flop through look-up table to another flip-flop to an external
output, only the path from the first flip-flop through the look-up
table to the second flip-flop is measured for "Minimum period".
what exactly does "Maximum pin delay" measure, and can i use it as a performance measure?
I didn't see this in the report, but "Minimum input arrival before
clock" is the required setup time from the worst case top-level design
input to the clock. In your case it is less than the "Minimum
period" so it may be possible to run the design at the maximum clock
frequency specified. Again after synthesis these are only
estimates, you need to place and route the design to get hard
numbers. Also if your design as synthesized represents only a
portion of a larger design, the input and output timings may be
significantly different, as they may not represent signals going on or
off of the FPGA. Similarly "Maximum output required time
after clock" refers to the delay from the clock to external outputs of
the top-level design for the worst case pins.
HTH,
Gabor
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09-24-2007 05:58 AM
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Re: Synthesis Help
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saed_swedan80
Visitor
Posts: 4
Registered: 09-23-2007
Message 4 of 7
Viewed 5,392 times
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this is an addition to the previous post.
My implementation consists of 3 main modules, a Control Unit (CU), an Register Unit (SU), an Adder Unit (AU), and a Top level Module to connect them all. CU and RU are squential (Clocked), and AU is completely combinational.
My problem is that when I Synthesize the Top level Module I get:
"
Minimum period: 4.129ns (Maximum Frequency: 242.202MHz)
Minimum input arrival time before clock: 2.961ns
Maximum output required time after clock: 2.570ns
Maximum combinational path delay: No path found
"
And when I Synthesize AU I get:
"
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 23.301ns
"
So, My Question is, If "Minimum period" could be used instead of "Maximum combinational path delay", shouldn't the "Minimum period" for the Top Level be Larger than "Maximum combinational path delay" for the adder unit? and if "Minimum period" can't be used instead of "Maximum combinational path delay", what should i do?
Please reply asap, this is an urgent matter...
Thanks in advance....
Regards,
Saed Swedan
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10-14-2007 06:57 PM
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Re: Synthesis Help
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rahul.hariharan
Visitor
Posts: 9
Registered: 06-05-2008
Message 7 of 7
Viewed 3,808 times
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Can you please again highlight on the message "Maximum combinational path delay: No path found". I am get this message in synthesis report of few of my designs.. Do you mean that we get this message when there is pure combinational circuit between the input and output of the design???
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06-05-2008 04:29 PM
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