Community Forums

1,099 Members Online 166K Discussions 48.8K Solutions

Community Activity

	Remake of some electronic device by Anomalia Newbie in Xilinx Evaluation Boards 08-08-2020 0 0	0	0
	Logic utilization reduction by hugobpontes Observer in FPGA Configuration 08-08-2020 0 2	0	2
	Zynq 7000 MIO[9] by pnefos Visitor in Other FPGA Architecture 08-08-2020 0 1	0	1
	vivado调用modelsim仿真时，对所有文件进行分析 by Kelvin001 Newbie in Vivado 08-08-2020 0 2	0	2
	Is there a way to write default I/O Std into xdc files automatically when saving IO port from scheme by soyaohnishi Visitor in Vivado Debug and Power Estimation Tools 08-08-2020 0 1	0	1
	Cannot install Guest Additions CD image in VirtualBox by knugent Adventurer in Embedded Linux 08-08-2020 0 5	0	5
	Creating a C++ application in Vitis by 3daerospace Newbie in AI and Vitis AI 08-08-2020 0 6	0	6
	cannot find loop detail in synthesis by liao_zi_lan@qq.com Newbie in High-Level Synthesis (HLS) 08-08-2020 0 0	0	0
	利用block memory generator产生单口RAM读数据问题 by huyijun Visitor in 嵌入式工具&软件开发 08-08-2020 0 3	0	3
	Vivado 2020.1 TCL The object 'run' does not have a property 'STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT'. by ellorens Visitor in Synthesis 08-08-2020 0 2	0	2
	RISC V Simulation by Sat Visitor in FPGA Configuration 08-08-2020 0 0	0	0
	Yolov4 support to DNNDK by sai.chittajallu Participant in AI and Vitis AI 08-08-2020 0 21	0	21
	AXi Chip2Chip config error by huanghaibin Explorer in 互连 08-08-2020 0 15	0	15
	artix 7- MIG ref_clk connected to gnd by avinashc Adventurer in Memory Interfaces and NoC 08-07-2020 0 4	0	4
	can xilinx zynq-7000 suport 3D convolution by ricardoluffy Newbie in AI Engine, DSP IP and Tools 08-07-2020 0 5	0	5
	asy fifo empty and full is pushed high at same time by andy_zhang Visitor in Processor System Design and AXI 08-07-2020 0 2	0	2
	Vivado UVM Simulation Error: pop_front is not declared under prefix... by epsage Newbie in Simulation and Verification 08-07-2020 0 1	0	1
	[Bug] Automatic variables make xsim of Vivado 2020.1 crash by a_bert Participant in Simulation and Verification 08-07-2020 0 2	0	2
	Appropriate license for software developer (Linux drivers for FPGA firmware)? by dreadedhill Visitor in Installation and Licensing 08-07-2020 0 1	0	1
	force_replication_on_nets question by khyu Observer in Implementation 08-07-2020 0 0	0	0
	Why doesn't USER_SLR_ASSIGNMENT apply? by gjwlstjr Visitor in Alveo™ Accelerator Cards 08-07-2020 0 0	0	0
	zcu102开发板使用两个cortex a53核进行通信以及DDR4划分问题 by Sparkwang1 Visitor in 嵌入式工具&软件开发 08-07-2020 0 1	0	1
	Uartlite: Receive buffer stuck in infinite loop by shrinir Visitor in Embedded Development Tools 08-07-2020 0 0	0	0
	Command Line Tools in Vitis by I_Promise_I_Am_ Newbie in Vitis Acceleration, SDAccel, SDSoC 08-07-2020 0 0	0	0
	Vivado Block design Clock error by Shankar Visitor in Implementation 08-07-2020 0 1	0	1
	AXI Chip-to-Chip仿真 by huanghaibin Explorer in 其他IP应用 08-07-2020 0 9	0	9
	Update the bitstream, after making changes in the elf file, without re-synthesizing and re-implementing by vmistry1 Visitor in Embedded Development Tools 08-07-2020 0 4	0	4
	Connecting a FPGA to an ASIC (similar to a Hybrid ASIC and FPGA architecture) by pfrrodrigues Visitor in Design Methodologies and Advanced Tools 08-07-2020 0 3	0	3
	board is not present in DTG by arman Newbie in Embedded Linux 08-07-2020 0 1	0	1
	Xsct Problem : Cortex-A53 #0 (No Power) by esraaltun Observer in Embedded Linux 08-07-2020 0 3	0	3

New solutions

Subject

Author

axi stream T valid

FSBL File not found

Artix-7 LVCMOS1.8 standard

Vivado Download Centre Name and Address Verificati...

Dongle linux FlexId

Top Kudoed Authors

Member

Kudos