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Community Forums

Subject	Author	Latest Post
Floating point IP : reset malbehavior Simulation and Verification	mariem_@fsm.12-34	‎08-20-2017 03:57 AM by mariem_@fsm.12-34
Zynq UltraScale+ MPSoC ISerdess3 utilisation UltraScale Architecture™	vova2211	‎08-20-2017 12:28 AM by vova2211
ila doesn't display "waiting for trigger". after ... Simulation and Verification	tchin123	‎08-20-2017 02:26 AM by thakurr
Ultrascale implement issue (ERROR: [Place 30-843]) Implementation	quincyq2003	‎08-19-2017 06:41 PM by hpoetzl
ZCU102 Error while building recipe petalinux-image... Embedded Linux	sandeepdutta	‎08-19-2017 05:57 PM by sandeepdutta

	Title	Posts
	Xcell Daily Blog Latest Topic - Digilent’s new Arty S7 Dev Board based on Spartan-...	2573
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About Our Community

(3 Items)

	Title	Posts
	Announcements Latest announcements, new features, and usage. Latest Topic - Congratulations to our June Top Solution and Top K...	1458
	Welcome & Join New to the Community? Get started by checking out our community guidelines and introduce yourself to the community. Latest Topic - VHDL design help	32120
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Programmable Devices

(6 Items)

	Title	Posts
	UltraScale Architecture™ Discuss Xilinx UltraScale Architecture including Kintex UltraScale, and Virtex UltraScale. Latest Topic - Zynq UltraScale+ MPSoC ISerdess3 utilisation	2605
	7 Series FPGAs Discuss Xilinx® Unified Architecture including Artix™-7, Kintex™-7, Spartan™-7, and Virtex®-7. Latest Topic - VHDL Code of SPI to interface with TI DAC8775	17933
	Virtex® Family FPGAs Discuss Virtex® Family FPGAs, including Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Virtex/E/EM, and mature devices. Latest Topic - Virtex 6 XCLVLX130T : EMAC and DP83867 PHY, how to...	20242
	Spartan® Family FPGAs Discuss Spartan® Family FPGAs, including Spartan-6, Spartan-3A DSP, Spartan-3AN, Spartan-3A, Spartan-3E, Spartan-3, Spartan-IIE, Spartan-II, Spartan/XL, and mature devices. Latest Topic - Spartan - 3A ADC and DAC interface	30512
	Xilinx Boards and Kits Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs. Latest Topic - ZCU102 Example dm10	14974
	Configuration Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, iMPACT, and Vivado Device Programmer software related topics. Latest Topic - should I give gated clock to startupe3	4446

Design Tools

(11 Items)

	Title	Posts
	Installation and Licensing Discuss topics involving installation, licensing, updates, and operating system support for all products in the Vivado™ Design Suite and the ISE Design Suite™. Latest Topic - 2015.2 License Error	17142
	Synthesis Discuss topics involving HDL synthesis tools and practices, including Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips. Latest Topic - How to reset a varible in case statement	21184
	Simulation and Verification Discuss topics involving simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators, and formal verification. Latest Topic - Floating point IP : reset malbehavior	18023
	Implementation Discuss topics involving design implementation tools and practices, including Vivado™ Implementation, Translate, Map, Place and Route, SmartXplorer, and FPGA Editor. Latest Topic - Ultrascale implement issue (ERROR: [Place 30-843])	17158
	Design Entry Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics. Latest Topic - ip_user_files/ipstatic filename conflicts	12372
	Timing Analysis Discuss topics involving timing analysis including tools and best practices, including Timing closure and XDC Timing Analyzer™, TRACE™, Timing Constraints, and Speed Files. Latest Topic - How can I fix this timing error, please?	11816
	Vivado TCL Community Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions. Latest Topic - link_design -mode default -reconfig_partitions {in...	4703
	High-Level Synthesis (HLS) Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx All Programmable devices. Latest Topic - HLS AXI4-lite problem in Linux	9206
	Design Methodologies and Advanced Tools Discuss the UltraFast Design Methodology, Design Methodology Checklist, RTL Coding styles, Baselining, Partial Reconfiguration and Design Preservation flows, design planning tools and flows. Latest Topic - PR - area between two clock regions	4157
	SDAccel Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs. Latest Topic - Device-side enqueue	1095
	Design Tools - Others Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, Power Estimation tools, iMPACT, and others. Latest Topic - SDK 2016.4 14:03:13 ERROR : (XSDB Server)ERROR: [H...	9546

Embedded Systems

(6 Items)

	Title	Posts
	Embedded Development Tools Discuss embedded software development tools including IPI, SDK, EDK, Compiler and Debugger Tools. Latest Topic - GPIO 4switches	40347
	Embedded Processor System Design Discuss processors, peripherals, AXI, and related processor system design topics for the Zynq 7000 Family PS, MicroBlaze and PowerPC and PicoBlaze processors. Latest Topic - Unable to stop Microblaze	19685
	Embedded Linux Discuss embedded Linux topics for Xilinx FPGAs including PetaLinux SDK, Xilinx Open Source Libraries, and Commercial Linux from Xilinx Ecosystem vendors. Latest Topic - ZCU102 Error while building recipe petalinux-image...	20490
	Zynq All Programmable SoC Discuss silicon related questions about the Zynq All Programmable SoC including programmable fabric, board design, packaging, power, and related topics. Latest Topic - Zynq MPSoC Builtin AXI Performance Monitors	13287
	SDSoC Development Environment Discuss SDSoC Development Environment related topics and issues. Latest Topic - Getting started w. reVISION - whats needed?	967
	OpenAMP Discuss OpenAMP project for Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze. Latest Topic - FreeRTOS not reponding to interrupts with AMP on A...	245

Intellectual Property

(5 Items)

	Title	Posts
	PCI Express Discuss topics on PCI Express. Latest Topic - How Set CRC Check for the PCIe V3.3	8615
	Networking and Connectivity Discuss Networking and connectivity IP cores including Ethernet, Aurora, JESD, CPRI, and related topics. Latest Topic - four lane PCS/PMA problem	10334
	Memory Interfaces Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII,LPDDR,MCB, and related topics. Latest Topic - DDR4 simulation issue with c0_ddr4_app_wdf_rdy = X	10191
	DSP and Video Discuss DSP tool- System Generator, DSP IPs such as error correction, filtering, telecommunications, wireless, Digital Signal Processing, mathematical functions and multimedia functions. It also covers questions on video imaging IPs and applications. Latest Topic - csi2(Tx or Rx) and dsi(Tx or Rx) for clk_p/clk_n l...	17083
	BRAM/FIFO Discuss IP including Block Memory Generator, FIFO Generator, Distributed Memory Generator, and ECC. Latest Topic - Latency Error in FIFO generator IP	2691

New solutions

Subject	Author
How to pass variables to DCM Spartan® Family FPGAs	pkiang
How can I fix this timing error, please? Timing Analysis	helmutforren
MicroBlaze KC705 2GB Embedded Processor System Design	igortf
What does this timing warning mean, please? Timing Analysis	helmutforren
10G PCS PMA multiple core instance Networking and Connectivity	floorbalint

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