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	CDMA is not transfering data from BRAM to DDR by lokesh_oepl Adventurer in Processor System Design and AXI 07-23-2021 0 4	0	4
	zcu106 SDI Passthrough Example design in vivado 2020.1 by Hrishikesh Adventurer in Video and Audio 07-23-2021 0 3	0	3
	Advanced Bootable Images Storage Settings Does Not Exist by apadana1984 Observer in Embedded Linux 07-23-2021 0 4	0	4
	Petalinux fsbl build error : do_compile by SI Visitor in Embedded Linux 07-23-2021 0 1	0	1
	Deassertion of ap_vld on inputs causes core to work by embedded Advisor in High-Level Synthesis (HLS) 07-23-2021 0 1	0	1
	PS-PL DRAM discrepancy by anon12850 Visitor in Processor System Design and AXI 07-23-2021 0 8	0	8
	Inconsistent results between quantized model and deployed model after the compilation by yz87@rice.edu Visitor in AI and Vitis AI 07-23-2021 0 3	0	3
	Strange error from Vivado 2020.2 when trying to set IP block property by steedman Newbie in Design Entry 07-23-2021 0 0	0	0
	Ultrascale+ PCI requester completion bad requester ID by cgonzo Visitor in PCIe and CPM 07-23-2021 0 3	0	3
	Device tree configuration for external PHY by suvrat13 Visitor in Embedded Linux 07-23-2021 0 2	0	2
	Reading and Writing to Register in one clock by pouya_hwsw Newbie in High-Level Synthesis (HLS) 07-23-2021 0 4	0	4
	Converting Fixed-Point Register into Float by pouya_hwsw Newbie in High-Level Synthesis (HLS) 07-23-2021 0 1	0	1
	Block design container Bugs report (VIVADO/Petalinux 2021.1) by ali_flt Adventurer in Design Entry 07-23-2021 0 0	0	0
	Is create_generated_clock needed? by zhangfeng Contributor in Timing Analysis 07-23-2021 0 2	0	2
	Vivado HLS csim compilation error related to ap_fixed by unnamedCapsLock Newbie in High-Level Synthesis (HLS) 07-23-2021 0 0	0	0
	Missing TLAST from AXI 1G/2.5G Ethernet Subsystem (7.1) core (not same as 7.2 bug fix))) by h.ho@saphtonics.com Visitor in Ethernet 07-23-2021 0 6	0	6
	XDMA transfers not completing when using MM2S IP by olsene01 Visitor in PCIe and CPM 07-23-2021 0 0	0	0
	FSBL Status = 0xA011 by fincs Adventurer in Processor System Design and AXI 07-23-2021 0 4	0	4
	在zcu104上运行vitis AI的VART sample出错 by lpc Contributor in Vitis, HLS, Alveo, ML以及其他软件应用 07-23-2021 0 6	0	6
	Vitis AI在哪里下载 by Lecheng_Huang21 Newbie in Vitis, HLS, Alveo, ML以及其他软件应用 07-23-2021 0 0	0	0
	Identify product authenticity XC7A200T-1FBG484C by zdct-01 Visitor in FPGA Configuration 07-23-2021 0 3	0	3
	Error: "The input ports on this block must be driven by other Xilinx blocks" by dchevaliaa Visitor in AI Engine, DSP IP and Tools 07-23-2021 0 1	0	1
	Debugging Error in Xilinx SDK (Microblaze Processor) by Macattack Observer in Vivado Debug and Power Estimation Tools 07-23-2021 0 2	0	2
	Fast Fourier Transform 9.1 issue with output by mdiggitydey Visitor in Xilinx IP Catalog 07-23-2021 0 4	0	4
	Vitis AI 1.4 is live by gguasti Moderator in AI and Vitis AI 07-23-2021 0 0	0	0
	axi dma的AXI Control Stream和AXI Status Stream连接问题 by mrzhang_ Observer in 其他IP应用 07-23-2021 0 5	0	5
	Configuring I2C Switch using PS I2C in Baremetal by kbk21 Visitor in Processor System Design and AXI 07-23-2021 0 0	0	0
	nvme timeout, completion polled Vivado 2021.1, Petalinux 2021.01 by AntonRG Participant in PCIe and CPM 07-23-2021 0 10	0	10
	AXI CDMA BRAM to DDR transfer issue by micah_d Newbie in Processor System Design and AXI 07-23-2021 0 0	0	0
	Zynq UltraScale+ Xil_SyncAbortHandler - How to debug? by tim_severance Scholar in Embedded Development Tools 07-23-2021 0 1	0	1