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	hw_server by foreignpara Visitor in Embedded Development Tools 04-18-2021 0 1	0	1
	access u-boot from Petalinux (without build) by roymesi2 Adventurer in Embedded Linux 04-18-2021 0 1	0	1
	AXI Quad SPI has retern BRESP=10(SLV_ERR) when write 0x0000000A to SRR(BASE+0x40) register by ApertureElectro Participant in Processor System Design and AXI 04-18-2021 0 2	0	2
	6G-SDI and 4k HDMI on same MGT Quad by electribe Visitor in Serial Transceivers 04-18-2021 0 0	0	0
	Hold Violations on negedge flops - how to solve? by ldm_gk Participant in Timing Analysis 04-18-2021 0 5	0	5
	Vivado write_bitstream - ERROR: Unspecified I/O Standard by devParksogang Visitor in Simulation and Verification 04-18-2021 0 2	0	2
	Vivado write_bitstream - ERROR: Unspecified I/O Standard by devParksogang Visitor in Vivado Debug and Power Estimation Tools 04-18-2021 0 1	0	1
	Multistream Inference on Ultra 96 v2 using RTSP cameras by darshan007 Visitor in AI and Vitis AI 04-18-2021 0 1	0	1
	HLS hardware kernels hang by kvu1998 Newbie in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 0	0	0
	AXI Ethernet by Raghunath Visitor in Ethernet 04-18-2021 0 1	0	1
	XRT API vs Open CL API pros and cons by goahead97 Adventurer in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 2	0	2
	Installation error by srilatha Visitor in Installation and Licensing 04-18-2021 0 3	0	3
	Hold Time Violation on AXI 1G/2.5G Ethernet Subsystem with RGMII Interface by shrsmas0 Visitor in Ethernet 04-18-2021 0 1	0	1
	The download speed of the installation package is too slow by sen_hu Newbie in Installation and Licensing 04-18-2021 0 1	0	1
	Unused GTP quad columns in XC7A200T-2FB676I by Juanito Visitor in Serial Transceivers 04-18-2021 0 1	0	1
	Auto BRAM Depth Issue by fahadak69 Observer in Xilinx IP Catalog 04-18-2021 0 0	0	0
	Fan section getting only 5V instead of 12V by chethu Newbie in Xilinx Evaluation Boards 04-18-2021 0 1	0	1
	PyOpenCL and Python in Vitis 2020.2 by goahead97 Adventurer in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 2	0	2
	DDR3 memory banks with system clock bank selection by akarshana Adventurer in Memory Interfaces and NoC 04-18-2021 0 0	0	0
	SmartLynq (Model DLC20) screen shows nothing after update by sarojj7 Visitor in FPGA Configuration 04-18-2021 0 3	0	3
	where I find an example of using qdma axi4-stream h2c & c2h by ispyco Visitor in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 2	0	2
	VC709 MIG setting? by Carlos0u0 Visitor in Memory Interfaces and NoC 04-18-2021 0 0	0	0
	QSFP ports on Alveo through Vitis by jimd6776 Observer in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 1	0	1
	What is the target platform of Xilinx object files compiled with package_xo? by goahead97 Adventurer in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 2	0	2
	SLR blanks not getting populatedin Hardware emulation (wide_vadd project) by goahead97 Adventurer in Vitis Acceleration, SDAccel, SDSoC 04-18-2021 0 4	0	4
	Vitis-AI for Zynq7000 family devices by xrancano@alumnos.uvigo.es Contributor in AI and Vitis AI 04-18-2021 0 5	0	5
	Versal AI Core Series by khalil Visitor in Xilinx Evaluation Boards 04-18-2021 0 1	0	1
	ila trigger condition setting by mycstudy Visitor in Xilinx IP Catalog 04-18-2021 0 1	0	1
	IMPACT : Can't open /dev/parport0: No such file or directory by user123random Adventurer in FPGA Configuration 04-18-2021 0 1	0	1
	ISERDES3 时序违规 by zhaowei1996 Observer in Versal and UltraScale 架构 04-18-2021 0 0	0	0