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	使用xlinx GTP收发器，验证10G光纤通信 by kaiseradler Adventurer in 互连 05-11-2021 0 20	0	20
	百度的开发板fz3B by kaiseradler Adventurer in 嵌入式硬件系统开发 05-11-2021 0 7	0	7
	Failure by building a Platform for CortexM3 in Vitis by ivkome Visitor in Embedded Development Tools 05-11-2021 0 0	0	0
	Error building platform on vitis by ivkome Visitor in Embedded Development Tools 05-11-2021 0 11	0	11
	UG947中的困惑 by blackbird Visitor in Vivado 05-11-2021 0 8	0	8
	About zstd in the Vitis data_compress Library by BiscuitsColonel Visitor in Vitis Acceleration, SDAccel, SDSoC 05-11-2021 0 0	0	0
	Updatemem flow problem by khyu Contributor in Implementation 05-11-2021 0 3	0	3
	Is there a common platform file for Zynq UltraScale+ MPSoC AXU2CGB? by FingerRhymer Visitor in Vitis Acceleration, SDAccel, SDSoC 05-11-2021 0 0	0	0
	Please correct the errors and send your information again. We cannot fulfill your request as your account has failed export compliance verification. by uzair12 Newbie in Xilinx Evaluation Boards 05-11-2021 0 0	0	0
	Partial input delay by Anonymous Not applicable in Synthesis 05-11-2021 0 5	0	5
	Using SDI and VCU on XCZU4EV by yellowd Explorer in Video and Audio 05-11-2021 0 4	0	4
	ZCU208 - Incorrect ADC Spectrum Displayed on GUI by takaka Newbie in Versal and UltraScale Architecture™ 05-11-2021 0 1	0	1
	Not able to mount root fs during SD boot on custom board, petalinux 2020.1 by garging Visitor in Embedded Linux 05-11-2021 0 2	0	2
	Reset and clocking of IDELAYCTRL and ODELAYE3 by mildred Visitor in Versal and UltraScale Architecture™ 05-11-2021 0 18	0	18
	XSCT command-line with no Xvfb by mjander3 Visitor in Embedded Development Tools 05-11-2021 0 3	0	3
	Spartan II (XC2S100-5FG256I) Discontinuation by PabloI Newbie in FPGA Configuration 05-11-2021 0 0	0	0
	How do I set USE_AMP=1 in a Vitis project by milosoftware Scholar in OpenAMP 05-11-2021 0 0	0	0
	Timing violations for tdm to tdm paths with Higher clock skew + SLR crossing by vian Visitor in Timing Analysis 05-11-2021 0 1	0	1
	ZCU104 boot options by Calvin Participant in Embedded Development Tools 05-11-2021 0 1	0	1
	U50, XDMA driver problem by vconst89 Adventurer in Alveo™ Accelerator Cards 05-11-2021 0 3	0	3
	Read&write to the same HBM bank by Yu Visitor in High-Level Synthesis (HLS) 05-11-2021 0 2	0	2
	Vitis build failure after updating XSA file by Nissan Visitor in Embedded Development Tools 05-11-2021 0 14	0	14
	Vitis 2020.2 and git tutorial by garengllc2 Observer in Embedded Development Tools 05-11-2021 0 2	0	2
	Vitis project and GIT by Nissan Visitor in Embedded Development Tools 05-11-2021 0 4	0	4
	Example design not wroking by vhdlveri123 Observer in Serial Transceivers 05-11-2021 0 6	0	6
	Run Vitis-AI vai_q_tensorflow quantize error with use pre-trained model of tensorflow by mkchan Contributor in Vitis, HLS, Alveo, ML以及其他软件应用 05-11-2021 0 1	0	1
	10G/25G Ethernet subsystem IP 授权 by sdersder Explorer in Vivado 05-11-2021 0 6	0	6
	求助：zynq7100，网络PHY使用TI DP83869，启动LINUX时总报错：Cannot find device “ETH0” by ddk Visitor in 嵌入式工具&软件开发 05-11-2021 0 12	0	12
	How to Version Control Vitis Projects by obruend Visitor in Embedded Development Tools 05-11-2021 0 10	0	10
	ML507 RS232 by allison_z Newbie in Xilinx评估板 05-11-2021 0 0	0	0