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Community Forums

Subject	Author	Latest Post
Questions about DDS ip core phase offst 7 Series FPGAs	keivnlee_1002	‎06-24-2017 12:33 AM by keivnlee_1002
How to design with IP cores Design Methodologies and Advanced Tools	g_arvind	‎06-24-2017 12:13 AM by hbucher
Error when running zcu102 swaccel-trd-2016-4 Xilinx Boards and Kits	danpianji88	‎06-24-2017 01:28 AM by danpianji88
SDSoC Development Environment Demo SDSoC Development Environment	heyuning	‎06-23-2017 10:41 PM by hbucher
Block design-----Create Inteface Port mode selecti... UltraScale Architecture™	alex_sun	‎06-24-2017 12:40 AM by a_chami

	Title	Posts
	Xcell Daily Blog Latest Topic - Vault over the Memory Wall. New White Paper discus...	2470
	Technical Blog Technical Blog for Tips and Tricks on Xilinx Tools and Products. Latest Topic - Synthesis going Out-of-Date for Unrelated Changes	16

About Our Community

(3 Items)

	Title	Posts
	Announcements Latest announcements, new features, and usage. Latest Topic - Accepted Solutions Week!	1454
	Welcome & Join New to the Community? Get started by checking out our community guidelines and introduce yourself to the community. Latest Topic - Read Memory Command MRD in TCL Variable	30486
	General Technical Discussion Discuss new Xilinx products, applications, and solutions. If you have a technical inquiry please search our community or browse our technical categories such as Programmable Devices or Embedded Solutions. Latest Topic - System Generator GUI Socket Server Timeout	24398

Programmable Devices

(6 Items)

	Title	Posts
	UltraScale Architecture™ Discuss Xilinx UltraScale Architecture including Kintex UltraScale, and Virtex UltraScale. Latest Topic - Block design-----Create Inteface Port mode selecti...	2294
	7 Series FPGAs Discuss Xilinx® Unified Architecture including Artix™-7, Kintex™-7, Spartan™-7, and Virtex®-7. Latest Topic - Questions about DDS ip core phase offst	17147
	Virtex® Family FPGAs Discuss Virtex® Family FPGAs, including Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Virtex/E/EM, and mature devices. Latest Topic - how to implement the GTECH synthesized netlist and...	20211
	Spartan® Family FPGAs Discuss Spartan® Family FPGAs, including Spartan-6, Spartan-3A DSP, Spartan-3AN, Spartan-3A, Spartan-3E, Spartan-3, Spartan-IIE, Spartan-II, Spartan/XL, and mature devices. Latest Topic - Implement low/high pass filter using FIR compiler ...	30266
	Xilinx Boards and Kits Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs. Latest Topic - Error when running zcu102 swaccel-trd-2016-4	14558
	Configuration Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, iMPACT, and Vivado Device Programmer software related topics. Latest Topic - Kintex-7 BPI Programming Erase Timeout	4170

Design Tools

(11 Items)

	Title	Posts
	Installation and Licensing Discuss topics involving installation, licensing, updates, and operating system support for all products in the Vivado™ Design Suite and the ISE Design Suite™. Latest Topic - IP licensing and functionality	16701
	Synthesis Discuss topics involving HDL synthesis tools and practices, including Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips. Latest Topic - Synthesis Failed with Vivado 2017 series	20602
	Simulation and Verification Discuss topics involving simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators, and formal verification. Latest Topic - setting ILA property C_EN_STRG_QUAL to true causes...	17526
	Implementation Discuss topics involving design implementation tools and practices, including Vivado™ Implementation, Translate, Map, Place and Route, SmartXplorer, and FPGA Editor. Latest Topic - shiftout1 and shiftout2 not connected error	16713
	Design Entry Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics. Latest Topic - touch file	11968
	Timing Analysis Discuss topics involving timing analysis including tools and best practices, including Timing closure and XDC Timing Analyzer™, TRACE™, Timing Constraints, and Speed Files. Latest Topic - Understanding ASYNC_REG attribute	11454
	Vivado TCL Community Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions. Latest Topic - export BRAM locations into *.MMI file	4538
	High-Level Synthesis (HLS) Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx All Programmable devices. Latest Topic - Microbalze stalled on FSL access.	8656
	Design Methodologies and Advanced Tools Discuss the UltraFast Design Methodology, Design Methodology Checklist, RTL Coding styles, Baselining, Partial Reconfiguration and Design Preservation flows, design planning tools and flows. Latest Topic - How to design with IP cores	4104
	SDAccel Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs. Latest Topic - SDAccel hw_emu problem: Segmentation fault (c...	953
	Design Tools - Others Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, Power Estimation tools, iMPACT, and others. Latest Topic - setting ILA property C_EN_STRG_QUAL to true causes...	9383

Embedded Systems

(6 Items)

	Title	Posts
	Embedded Development Tools Discuss embedded software development tools including IPI, SDK, EDK, Compiler and Debugger Tools. Latest Topic - I2C Pause issue	39831
	Embedded Processor System Design Discuss processors, peripherals, AXI, and related processor system design topics for the Zynq 7000 Family PS, MicroBlaze and PowerPC and PicoBlaze processors. Latest Topic - different memoryviews from different targets	19322
	Embedded Linux Discuss embedded Linux topics for Xilinx FPGAs including PetaLinux SDK, Xilinx Open Source Libraries, and Commercial Linux from Xilinx Ecosystem vendors. Latest Topic - zcu102 intermittent boot problems	19416
	Zynq All Programmable SoC Discuss silicon related questions about the Zynq All Programmable SoC including programmable fabric, board design, packaging, power, and related topics. Latest Topic - Expanding the RAM connected to SoC	12722
	SDSoC Development Environment Discuss SDSoC Development Environment related topics and issues. Latest Topic - SDSoC Development Environment Demo	857
	OpenAMP Discuss OpenAMP project for Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze. Latest Topic - Could run openmp on quad-core?	228

Intellectual Property

(5 Items)

	Title	Posts
	PCI Express Discuss topics on PCI Express. Latest Topic - Difference between AXI Lite Master and DMA Bypass ...	8417
	Networking and Connectivity Discuss Networking and connectivity IP cores including Ethernet, Aurora, JESD, CPRI, and related topics. Latest Topic - aurora_64b66b (11.2) max line rate 6.6Gbps for XC7...	10122
	Memory Interfaces Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII,LPDDR,MCB, and related topics. Latest Topic - Interfacing DDR3 memory with kintex 7 using MIG	10042
	DSP and Video Discuss DSP tool- System Generator, DSP IPs such as error correction, filtering, telecommunications, wireless, Digital Signal Processing, mathematical functions and multimedia functions. It also covers questions on video imaging IPs and applications. Latest Topic - JESD204B tx_reset out type	16782
	BRAM/FIFO Discuss IP including Block Memory Generator, FIFO Generator, Distributed Memory Generator, and ECC. Latest Topic - How to set CONFIG.MEM_WIDTH from the IP tcl script...	2606

New Solutions

Subject	Author
bpadd doesn't set breakpoints to relocated address... Embedded Development Tools	aionios
SDAccel and Vivado HLS SDAccel	gdg
ERROR: [VRFC 10-149] 'unsigned' is not compiled in... Simulation and Verification	bitbang
Video Processing Subsystem - interlace Size Regist... DSP and Video	ggrummer
IO placement is infeasible. Number of unplaced ter... Implementation	naz_rb

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Subject	Kudos
Using Amazon AWS cloud to run Vivado remotely	5
Re: Trouble creating Linux Application in SDK 2016...	3
Re: Problem with Vivado 2017.1 and Visual Studio 2...	3
Re: Vivado 2017.1 Crashed When Opening Implemented...	3
Re: "IOB=TRUE" can not work	2