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Technical Blog for Tips and Tricks on Xilinx Tools and Products.
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About Our Community
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Latest announcements, new features, and usage.
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New to the Community? Get started by checking out our community guidelines and introduce yourself to the community.
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Discuss new Xilinx products, applications, and solutions. If you have a technical inquiry please search our community or browse our technical categories such as Programmable Devices or Embedded Solutions.
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Programmable Devices
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Discuss Xilinx UltraScale Architecture including Kintex UltraScale, and Virtex UltraScale.
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Discuss Xilinx® Unified Architecture including Artix™-7, Kintex™-7, Spartan™-7, and Virtex®-7.
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Discuss Virtex® Family FPGAs, including Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Virtex/E/EM, and mature devices.
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Discuss Spartan® Family FPGAs, including Spartan-6, Spartan-3A DSP, Spartan-3AN, Spartan-3A, Spartan-3E, Spartan-3, Spartan-IIE, Spartan-II, Spartan/XL, and mature devices.
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Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs.
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Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, iMPACT, and Vivado Device Programmer software related topics.
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Design Tools
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Discuss topics involving installation, licensing, updates, and operating system support for all products in the Vivado™ Design Suite and the ISE Design Suite™.
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Discuss topics involving HDL synthesis tools and practices, including Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips.
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Discuss topics involving simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators, and formal verification.
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Discuss topics involving design implementation tools and practices, including Vivado™ Implementation, Translate, Map, Place and Route, SmartXplorer, and FPGA Editor.
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Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics.
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Discuss topics involving timing analysis including tools and best practices, including Timing closure and XDC Timing Analyzer™, TRACE™, Timing Constraints, and Speed Files.
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Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions.
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Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx All Programmable devices.
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Discuss the UltraFast Design Methodology, Design Methodology Checklist, RTL Coding styles, Baselining, Partial Reconfiguration and Design Preservation flows, design planning tools and flows.
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Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs.
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Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, Power Estimation tools, iMPACT, and others.
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Embedded Systems
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Discuss embedded software development tools including IPI, SDK, EDK, Compiler and Debugger Tools.
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Discuss processors, peripherals, AXI, and related processor system design topics for the Zynq 7000 Family PS, MicroBlaze and PowerPC and PicoBlaze processors.
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Discuss embedded Linux topics for Xilinx FPGAs including PetaLinux SDK, Xilinx Open Source Libraries, and Commercial Linux from Xilinx Ecosystem vendors.
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Discuss silicon related questions about the Zynq All Programmable SoC including programmable fabric, board design, packaging, power, and related topics.
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Discuss SDSoC Development Environment related topics and issues.
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Discuss OpenAMP project for Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze.
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Intellectual Property
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Discuss topics on PCI Express.
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Discuss Networking and connectivity IP cores including Ethernet, Aurora, JESD, CPRI, and related topics.
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Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII,LPDDR,MCB, and related topics.
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Discuss DSP tool- System Generator, DSP IPs such as error correction, filtering, telecommunications, wireless, Digital Signal Processing, mathematical functions and multimedia functions. It also covers questions on video imaging IPs and applications.
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Discuss IP including Block Memory Generator, FIFO Generator, Distributed Memory Generator, and ECC.
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