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karan_jasani

10G/25G Ethernet Subsystem tx_disable and tx_fault signal connection in IP Core

by Visitor karan_jasani Visitor in Xilinx IP Catalog 05-25-2020
0 0
0
0
alonsosara44@gmail.com

Xen Standalone guest

by Observer alonsosara44@gmail.com Observer in Embedded Development Tools 05-25-2020
0 0
0
0
painkil

Bit Extractor code results no_clock and unconstrained_internal_endpoints

by Observer painkil Observer in Timing Analysis 05-25-2020
0 2
0
2
joneylixm

Xilinx Zynq UltraScale+ MPSoCs ZU3 rtc驱动问题

by Newbie joneylixm Newbie in 嵌入式 工具&软件开发 05-25-2020
0 0
0
0
kimchaex

ZCU102 boot failure (DPU-TRD Vivado tutorial)

by Contributor Contributor in Embedded Linux 05-25-2020
0 2
0
2
drsdrb

新建IP核的似乎没有作用

by Observer drsdrb Observer in Vitis, HLS, Alveo, ML以及其他软件应用 05-25-2020
0 4
0
4
Jiasen

Problem with Creating platform on Vitis 2019.2

by Visitor Jiasen Visitor in Vitis Acceleration, SDAccel, SDSoC 05-25-2020
0 1
0
1
JM_Park

How can I access memory using Petalinux 2018.3 user application in zcu102

by Visitor JM_Park Visitor in Embedded Linux 05-25-2020
0 1
0
1
liweizhong

工程在VIVADO 2019版本综合后出现这样的告警，请专家看看。

by Observer liweizhong Observer in Vivado 05-25-2020
0 2
0
2
xrancano@alumnos.uvigo.es

Model-Zoo repository: Are the models compatible with ZedBoard?

by Observer xrancano@alumnos.uvigo.es Observer in AI and Vitis AI 05-25-2020
0 1
0
1
wangzy0327

Vitis_Accel_Examples如何添加新的cpp，如何解决ERROR:kernel 'vadd' not found

by Visitor wangzy0327 Visitor in Vitis, HLS, Alveo, ML以及其他软件应用 05-25-2020
0 3
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3
sunkim

about GTY bandwidth for ZU11EG.

by Participant sunkim Participant in Serial Transceivers 05-25-2020
0 6
0
6
v_robert

Vitis AI dpu abnormal low performance

by Visitor v_robert Visitor in AI and Vitis AI 05-25-2020
0 0
0
0
sunzengzhen

difference between PCIe PHY IP Equalization Interface Ports and the PIPE specification

by Newbie sunzengzhen Newbie in PCIe and CPM 05-25-2020
0 0
0
0
Abner

How to finetune 8-bit yolov3 caffemodel after quantization with DNNDK-V1.4?

by Newbie Abner Newbie in AI and Vitis AI 05-25-2020
0 3
0
3
mu_yu

sdx工具编译完成代码后，如何测试功耗？

by Adventurer Adventurer in 其他工具 05-25-2020
0 2
0
2
pra_shi

Convert the 4 lanes to 1 lane AXI interface

by Visitor pra_shi Visitor in Processor System Design and AXI 05-25-2020
0 2
0
2
eleni_palla

limit or prevent bram inferral in specific block

by Visitor eleni_palla Visitor in Other FPGA Architecture 05-25-2020
0 3
0
3
hipecal

报告时间和实际时间差距很大如何优化

by Observer hipecal Observer in Vitis, HLS, Alveo, ML以及其他软件应用 05-25-2020
0 1
0
1
turcant

Device tree overlay on ZCU102 : why isn't there an amba_pl in pl.dtsi ?

by Visitor turcant Visitor in Embedded Linux 05-25-2020
1 3
1
3
victor_dotouch

DMA多通道问题

by Explorer Explorer in 互连 05-25-2020
0 0
0
0
guodong_zl

zynq 7020 ps interrupt

by Adventurer Adventurer in 嵌入式 硬件系统开发 05-25-2020
0 2
0
2
Leo_ming

综合后出现找不到ip核 dcp、vhdl文件警告

by Visitor Leo_ming Visitor in Vivado 05-25-2020
0 3
0
3
dqwuf-2010

GTPE2_CHANNEL报错

by Explorer Explorer in 互连 05-25-2020
0 2
0
2
round_chen

ZynqMP can not set jumbo network

by Visitor round_chen Visitor in Embedded Linux 05-25-2020
0 0
0
0
mitch1993

Error while trying to use packaged IP from project with High Speed SelectIO

by Visitor mitch1993 Visitor in Design Entry 05-25-2020
0 3
0
3
chango_wupatec

We cannot fulfill your request as your account has failed export compliance verification.

by Newbie chango_wupatec Newbie in Installation and Licensing 05-25-2020
0 2
0
2
nzh

Can't add module to block design

by Observer nzh Observer in Design Methodologies and Advanced Tools 05-25-2020
0 1
0
1
tnareshnaresh7@gmail.com

idelayctrl 2 issues

by Adventurer Adventurer in Xilinx IP Catalog 05-25-2020
0 1
0
1
Bill_Ho

Recommendation for digital beamforming application

by Visitor Bill_Ho Visitor in Xilinx Evaluation Boards 05-25-2020
0 2
0
2
mlefevre

IDELAYE3 160 ps offset

by Adventurer Adventurer in Versal and UltraScale Architecture™ 05-25-2020
0 2
0
2
fred2019

System Performance Monitor for Zynq MPSoC

by Visitor fred2019 Visitor in Memory Interfaces and NoC 05-25-2020
0 5
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5
hw_zw@autobrain.cn

zynqmp ULTRA96-V2 配合ubuntu屏幕显示出错

by Participant hw_zw@autobrain.cn Participant in 嵌入式 工具&软件开发 05-25-2020
0 1
0
1
vishnu.k

Reason for PCIe stuck in polling compliance LTSSM state

by Observer vishnu.k Observer in PCIe and CPM 05-25-2020
0 15
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15
Leo_ming

.xdc文件编译顺序

by Visitor Leo_ming Visitor in Vivado 05-25-2020
0 1
0
1
Baruch

Trouble Quantizing Custom Model

by Visitor Baruch Visitor in AI and Vitis AI 05-25-2020
0 7
0
7
yolanda

QDMA Linux 内核驱动使用和调试指南

by Moderator Moderator in Xilinx 产品设计与功能调试技巧 05-25-2020
0 0
0
0
kbj1213

FPGA Schematic Datasheet

by Participant kbj1213 Participant in FPGA Configuration 05-24-2020
0 0
0
0
junweiz

赛灵思又一新款 16nm FPGA 面世， 专为速度而生！

by ChinaForumAdmin ChinaForumAdmin in Xilinx 热门新闻与活动 05-24-2020
0 0
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kharobangdo

TCL commands to change VIO variables to Text, LED, Active High Button, Toggle Buttons, change RADIX etc

by Adventurer Adventurer in Vivado Debug and Power Estimation Tools 05-24-2020
0 0
0
0
pdarshan

Generic(Baremetal) master/Linux remote

by Visitor pdarshan Visitor in OpenAMP 05-24-2020
0 2
0
2
lwf_breeze

petalinux编译报错

by Visitor lwf_breeze Visitor in 嵌入式 工具&软件开发 05-24-2020
0 5
0
5
niu_zun

自己设计的XC7Z100板子上电后DONE 信号不拉高

by Adventurer Adventurer in 其他FPGA器件架构 05-24-2020
0 12
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12
nagi12

Regarding i/o pins

by Visitor nagi12 Visitor in Implementation 05-24-2020
0 2
0
2
priya_mp

Regarding lwIP echo server in XSDK

by Visitor priya_mp Visitor in Ethernet 05-24-2020
0 10
0
10
deepg799

Xilinx model zoo - DPU architecture dependent

by Explorer Explorer in AI and Vitis AI 05-24-2020
0 0
0
0
sastliuwei

FPGA can not be configurated after encryption

by Observer sastliuwei Observer in FPGA Configuration 05-24-2020
0 2
0
2
deepg799

DPU-4096 dual-core | 7EV device

by Explorer Explorer in AI and Vitis AI 05-24-2020
0 6
0
6
debaere

How to force standard speed mode for SDIO connected to eMMC (2018.2) ?

by Participant debaere Participant in Embedded Linux 05-24-2020
0 0
0
0
hytera2015

x86cpu和zu1dr通过xdma多次收发数据包持续一段时间（半天或者一天，不确定），出现link_up变低，ltssm状态从10直接变为0

by Contributor Contributor in 互连 05-24-2020
0 0
0
0
jlhx

System Generator - Hardware Co-Simulation license error

by Visitor jlhx Visitor in AI Engine, DSP IP and Tools 05-24-2020
0 2
0
2
antonio.cerruto@astrel-instruments.com

SLVS-EC GTP programming

by Visitor antonio.cerruto@astrel-instruments.com Visitor in Serial Transceivers 05-24-2020
0 4
0
4
RickyTino

Vivado在Block Design中生成用户定义IP核时异常创建目录

by Visitor RickyTino Visitor in Vivado 05-24-2020
0 4
0
4
Ztone

Vitis-Tutorials mixing-c-rtl-kernel examples 报failed to load xclbin错误

by Observer Ztone Observer in Vitis, HLS, Alveo, ML以及其他软件应用 05-24-2020
0 3
0
3
lichangche

Xilinx ZynqMP jumbo frame not working

by Visitor lichangche Visitor in Ethernet 05-24-2020
0 6
0
6
gi4you

Virtex Ultrascal QSPI bootloader XIsf_Initialize failure

by Contributor Contributor in Processor System Design and AXI 05-24-2020
0 4
0
4
Leo_ming

删除.coe文件报错

by Visitor Leo_ming Visitor in Vivado 05-24-2020
0 1
0
1
wuyouniyanhu

The difference between the production version of VCU128 and the es1 version?

by Visitor wuyouniyanhu Visitor in Ethernet 05-24-2020
0 0
0
0
eg_suhm

ZCU102 PS端A53的单核重置问题

by Observer eg_suhm Observer in 嵌入式 硬件系统开发 05-24-2020
0 1
0
1
liweizhong

VIVADO 2015.4版本的工程升级到2019.1版本后综合没问题，但实现后出现以下告警，请帮忙看看，怎么解决

by Observer liweizhong Observer in Vivado 05-24-2020
0 8
0
8
chourching

使用ILA核抓的信号位数是25位，工程下载到板子并写入csv文件后，能否用MATLAB把信号读出来？

by Adventurer Adventurer in Vivado 05-24-2020
0 1
0
1
ysato

Output directly from RAM to Displayport

by Visitor ysato Visitor in Embedded Linux 05-24-2020
0 3
0
3
finish0404

VHDL's Struct of array in verilog

by Contributor Contributor in Synthesis 05-24-2020
0 0
0
0
wangzy0327

Vitis Accel Example 开发添加新的cpp文件，该如何在IDE里编译链接呢？

by Visitor wangzy0327 Visitor in Vitis, HLS, Alveo, ML以及其他软件应用 05-24-2020
0 0
0
0
Taylor-Liu

BUFIO與Iserdes2問題

by Visitor Taylor-Liu Visitor in 综合讨论 05-24-2020
0 1
0
1
marcowu

Multi Scaler(PG325) video data is not correct

by Observer marcowu Observer in Video and Audio 05-24-2020
0 3
0
3
MuzamilFarid

Axi dma, s2mm length register

by Visitor MuzamilFarid Visitor in FPGA Configuration 05-24-2020
0 1
0
1
dqwuf-2010

自己建的信号当时钟，不能用作FIFO的IP的CLK

by Explorer Explorer in 综合讨论 05-24-2020
0 1
0
1
chourching

下板调试出现问题 ERROR: [Labtools 27-3165] End of startup status: LOW

by Adventurer Adventurer in 其他FPGA器件架构 05-24-2020
0 10
0
10
dqwuf-2010

创建BD工程的时候， generate block design的作用是什么？

by Explorer Explorer in Vivado 05-24-2020
0 1
0
1
spann

SPI chipselect 0 already in use

by Visitor spann Visitor in Embedded Linux 05-24-2020
0 0
0
0
nzh

Failed to place design-DSP overutilization

by Observer nzh Observer in Implementation 05-24-2020
0 0
0
0
hiroaki4625

FFT IP Core performance for Artix

by Visitor hiroaki4625 Visitor in AI Engine, DSP IP and Tools 05-24-2020
0 2
0
2
danwwright0

specifying Aurora 8b10b GTP shared reference clocks on Artix-7

by Newbie danwwright0 Newbie in Serial Transceivers 05-24-2020
0 1
0
1
cntitan1982

IDE / Parallel ATA 模块或IP核

by Newbie cntitan1982 Newbie in 其他IP应用 05-24-2020
0 1
0
1
huanghaibin

AXI Chip-to-Chip仿真

by Explorer Explorer in 其他IP应用 05-24-2020
0 6
0
6
lzhao

Build the deep learning model structure with HLS. How to introduce the weight to the kernel?

by Contributor Contributor in AI and Vitis AI 05-24-2020
0 3
0
3
lgarrido@harris.com

Adding Python Packages to ZCU102 image

by Visitor lgarrido@harris.com Visitor in AI and Vitis AI 05-24-2020
0 7
0
7
1993833617@qq.com

zynq-7000双ARM核公用DDR地址分配问题

by Explorer Explorer in 嵌入式 工具&软件开发 05-24-2020
0 1
0
1
joe306

Symmetric Mulitprocessor using FreeRTOS?

by Scholar joe306 Scholar in Processor System Design and AXI 05-24-2020
0 6
0
6
umi

vivado2019.2在线调试无法捕捉信号

by Newbie umi Newbie in 嵌入式 硬件系统开发 05-24-2020
0 1
0
1
garfy123

How to disable/enable FCLK

by Observer garfy123 Observer in Embedded Linux 05-24-2020
0 10
0
10
alexis_jp

2019.2: Latches infinite slack and infered latches: is there any concerns?

by Adventurer Adventurer in Timing Analysis 05-24-2020
0 1
0
1
mesham

Aborting preceding dataflow regions

by Visitor mesham Visitor in High-Level Synthesis (HLS) 05-24-2020
0 1
0
1
alanmimms

Enum and reverse-from-usual bit order formals yield zero in instantiated module

by Visitor alanmimms Visitor in Simulation and Verification 05-24-2020
0 0
0
0
AliAlra

ODELAYE3

by Visitor AliAlra Visitor in Versal and UltraScale Architecture™ 05-24-2020
0 6
0
6
ramesh_ch3

Petalinux2019.2 kernel configuration problem in my PC

by Observer ramesh_ch3 Observer in Embedded Linux 05-24-2020
0 1
0
1
cwolfe

Installing Ubuntu on Zynq Ultrascale+ ZCU102

by Observer cwolfe Observer in Embedded Linux 05-24-2020
0 27
0
27
klumsde

Method for instantiating an entire L type slice

by Moderator Moderator in Other FPGA Architecture 05-24-2020
0 0
0
0
Lohil

Method for instantiating an entire L type slice

by Visitor Lohil Visitor in Design Entry 05-24-2020
0 0
0
0
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