UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Community
Title Posts
Blog

Xcell Daily Blog

2107
Blog

Technical Blog

Technical Blog for Tips and Tricks on Xilinx Tools and Products.
Latest Topic - Terminology for IP Flow
14
Title Posts
There are no unread messages in this message board

Announcements

Latest announcements, new features, and usage.
1431
There are no unread messages in this message board

Welcome & Join

New to the Community? Get started by checking out our community guidelines and introduce yourself to the community.
26277
There are no unread messages in this message board

General Technical Discussion

Discuss new Xilinx products, applications, and solutions. If you have a technical inquiry please search our community or browse our technical categories such as Programmable Devices or Embedded Solutions.
23523
Title Posts
There are no unread messages in this message board

UltraScale Architecture™

Discuss Xilinx UltraScale Architecture including Kintex UltraScale, and Virtex UltraScale.
1414
There are no unread messages in this message board

7 Series FPGAs

Discuss Xilinx® Unified Architecture including Artix™-7, Kintex™-7, Spartan™-7, and Virtex®-7.
14727
There are no unread messages in this message board

Virtex® Family FPGAs

Discuss Virtex® Family FPGAs, including Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Virtex/E/EM, and mature devices.
19975
There are no unread messages in this message board

Spartan® Family FPGAs

Discuss Spartan® Family FPGAs, including Spartan-6, Spartan-3A DSP, Spartan-3AN, Spartan-3A, Spartan-3E, Spartan-3, Spartan-IIE, Spartan-II, Spartan/XL, and mature devices.
29643
There are no unread messages in this message board

Xilinx Boards and Kits

Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs.
Latest Topic - AC701 Version 1.0 vs 2.0
13601
There are no unread messages in this message board

Configuration

Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, iMPACT, and Vivado Device Programmer software related topics.
3667

Design Tools

(11 Items)
Title Posts
There are no unread messages in this message board

Installation and Licensing

Discuss topics involving installation, licensing, updates, and operating system support for all products in the Vivado™ Design Suite and the ISE Design Suite™.
15356
There are no unread messages in this message board

Synthesis

Discuss topics involving HDL synthesis tools and practices, including Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips.
18912
There are no unread messages in this message board

Simulation and Verification

Discuss topics involving simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators, and formal verification.
16201
There are no unread messages in this message board

Implementation

Discuss topics involving design implementation tools and practices, including Vivado™ Implementation, Translate, Map, Place and Route, SmartXplorer, and FPGA Editor.
15258
There are no unread messages in this message board

Design Entry

Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics.
10821
There are no unread messages in this message board

Timing Analysis

Discuss topics involving timing analysis including tools and best practices, including Timing closure and XDC Timing Analyzer™, TRACE™, Timing Constraints, and Speed Files.
Latest Topic - set_max_delay
10357
There are no unread messages in this message board

Vivado TCL Community

Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions.
4143
There are no unread messages in this message board

High-Level Synthesis (HLS)

Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx All Programmable devices.
7160
There are no unread messages in this message board

Design Methodologies and Advanced Tools

Discuss the UltraFast Design Methodology, Design Methodology Checklist, RTL Coding styles, Baselining, Partial Reconfiguration and Design Preservation flows, design planning tools and flows.
3979
There are no unread messages in this message board

SDAccel

Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs.
Latest Topic - SDAccel Access in Nimbix
391
There are no unread messages in this message board

Design Tools - Others

Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, XPower Analyzer, iMPACT, and others
8884

Embedded Systems

(6 Items)
Title Posts
There are no unread messages in this message board

Embedded Development Tools

Discuss embedded software development tools including IPI, SDK, EDK, Compiler and Debugger Tools.
38292
There are no unread messages in this message board

Embedded Processor System Design

Discuss processors, peripherals, AXI, and related processor system design topics for the Zynq 7000 Family PS, MicroBlaze and PowerPC and PicoBlaze processors.
18215
There are no unread messages in this message board

Embedded Linux

Discuss embedded Linux topics for Xilinx FPGAs including PetaLinux SDK, Xilinx Open Source Libraries, and Commercial Linux from Xilinx Ecosystem vendors.
16969
There are no unread messages in this message board

Zynq All Programmable SoC

Discuss silicon related questions about the Zynq All Programmable SoC including programmable fabric, board design, packaging, power, and related topics.
11275
There are no unread messages in this message board

SDSoC Development Environment

Discuss SDSoC Development Environment related topics and issues.
443
There are no unread messages in this message board

OpenAMP

Discuss OpenAMP project for Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze.
199
Title Posts
There are no unread messages in this message board

PCI Express

Discuss topics on PCI Express.
7832
There are no unread messages in this message board

Networking and Connectivity

Discuss Networking and connectivity IP cores including Ethernet, Aurora, JESD, CPRI, and related topics.
9362
There are no unread messages in this message board

Memory Interfaces

Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII,LPDDR,MCB, and related topics.
9584
There are no unread messages in this message board

DSP and Video

Discuss DSP tool- System Generator, DSP IPs such as error correction, filtering, telecommunications, wireless, Digital Signal Processing, mathematical functions and multimedia functions. It also covers questions on video imaging IPs and applications.
Latest Topic - Fir filter blocking mode?
16021
There are no unread messages in this message board

BRAM/FIFO

Discuss IP including Block Memory Generator, FIFO Generator, Distributed Memory Generator, and ECC.
2359
Users Online
Currently online: 9 members 1,694 guests
Please welcome our newest community members:
Announcements
Chinese Community Forums

Check out the new Technical Blog for Tips and Tricks on Xilinx Tools and Products!


Before you post, please read our Community Forums Guidelines
Community Forums FAQ and Help
Monthly Recognition
Top Solution Authors
User Accepted Solutions Count
17
16
13
8
7
Top Kudoed Authors