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	XCZU3EG-1SFVC784I的上电时序 by wang_3130 Newbie in 嵌入式硬件开发 MPSoC & Zynq-7000 3m ago 0 2	0	2
	Segmentation fault with devmem by unir238 Newbie in Embedded Linux 7m ago 0 0	0	0
	How do I use Multi 10G(xxv) Ethernet with Mac address in zcu102? by hakjun Visitor in Networking and Connectivity 9m ago 0 2	0	2
	about XCZU3EG-1SFVC784I Power Sequence by wang_3130 Newbie in UltraScale Architecture™ 13m ago 0 2	0	2
	7020使用SD卡烧录PL端程序，第一次成功，当烧写第二次的时候出现会出现卡在烧录界面有时还会复位 by wjj@tronlong.com Visitor in 嵌入式硬件开发 MPSoC & Zynq-7000 14m ago 0 9	0	9
	Problem importing ReedMullerBasis_LUT_sp_r11_d32 from ISE to Vivado by bhawandeepsingh Visitor in Virtex® Family FPGAs 14m ago 0 0	0	0
	Why couldn't get the ip address when udp on petalinux only? by liwenz Explorer in Embedded Linux 18m ago 0 0	0	0
	Add coe files to FIR core by yf201306 Participant in DSP IP and Tools 21m ago 0 0	0	0
	7series Transceivers RXN/RXP 接続検出 by muraoka.nobuyoshi Newbie in 7 Series FPGAs 22m ago 0 0	0	0
	SDSoC ARRAY_PARTITION指令 by lucas_zyq Observer in SDx 25m ago 0 0	0	0
	Perform DMA transfer using 7 Series Integrated Block for PCI Express IP core by aliciachee Observer in PCI Express 27m ago 0 1	0	1
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	GTP/GTX通信，可以直接使用RJ45型接口+网线吗？ by lixw Participant in 7 Series FPGA & 其他 FPGA 器件 32m ago 0 2	0	2
	multiplier12.0 strange behavior by huagangxiaoyan Newbie in DSP IP and Tools 42m ago 0 0	0	0
	关于zynq petalinux移植的问题 by yr1076365487 Newbie in 嵌入式软件开发 43m ago 0 5	0	5
	vivado设计axi stream ip核 by jackzhao1234 Visitor in 互连 48m ago 0 1	0	1
	Does the ZynqMP cg series support PS DisplayPort output? by wen.k Visitor in Embedded Linux 48m ago 0 7	0	7
	Different Voltage for VCCO for XC3S50AN by khristofer_marfa.m@xim-21 Visitor in Spartan® Family FPGAs 54m ago 0 4	0	4
	乘法器IP使用 by huagangxiaoyan Newbie in 7 Series FPGA & 其他 FPGA 器件 55m ago 0 1	0	1
	disabling SRIO port by jacksonychia Visitor in Serial Transceivers 57m ago 0 0	0	0
	AR-68639 further information by meepmeep_beepbeep Visitor in Serial Transceivers an hour ago 0 13	0	13
	Simulation error: [VRFC 10-147] [VRFC 10-213] by andrieu Visitor in Simulation and Verification an hour ago 0 14	0	14
	Can't compile Xilinx IP Libraries by joseignaciob Newbie in Simulation and Verification an hour ago 0 1	0	1
	在bd中例化block memory generator时，为啥不能选择存储深度呢 by guodong_zl Observer in 嵌入式硬件开发 MPSoC & Zynq-7000 an hour ago 0 9	0	9
	sdk中基本数学函数 by guodong_zl Observer in 嵌入式软件开发 an hour ago 0 1	0	1
	HLS接口从RAM到FIFO告警 by yaoyinqi Visitor in 其他设计工具问题 an hour ago 0 3	0	3
	Spartan 7 MIG support for LPDDR devices by bivin Observer in Memory Interfaces an hour ago 0 7	0	7
	Zynq US+ PL Clock bufg_ps to MMCM by baf2099 Observer in Embedded Processor System Design an hour ago 0 0	0	0
	printf not working with with SDAccel 2018.2? by youad Visitor in SDAccel an hour ago 0 5	0	5
	Must I use block design if I want to use processing system on my zynq design? by castlephobia Newbie in Design Entry 2 hours ago 0 2	0	2

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