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	Failed to decode 8 h264 1920x1080p 30pfs using gstreamer. by keshava7887 Visitor in Video and Audio 08-05-2020 0 3	0	3
	关于petalinux2020.1 HDMI驱动显示问题 by xxzc Contributor in 嵌入式工具&软件开发 08-05-2020 0 6	0	6
	No timing signals generated from AXI4S to Video out IP by vishal_cg Observer in Video and Audio 08-05-2020 0 30	0	30
	makefile:87: recipe for target 'src/xf_corner_tracker_tb.o' failed by peanut Visitor in Vitis Acceleration, SDAccel, SDSoC 08-05-2020 0 1	0	1
	ZynqMP displayport monitor detection by matthew.singer@elbitsystems-us.com Observer in Video and Audio 08-05-2020 0 3	0	3
	use bootgen to generate bin in split mode by zhouchao_zhito Newbie in Xilinx Evaluation Boards 08-05-2020 0 0	0	0
	lwip TCP disconnect problem by Jonas_A Visitor in Ethernet 08-05-2020 0 2	0	2
	Xillybus issue by Denis Newbie in Embedded Linux 08-05-2020 0 0	0	0
	Ultrascale Block RAM ECC by fabio_malatesta Newbie in Versal and UltraScale Architecture™ 08-05-2020 0 1	0	1
	temac v.8 example design integration by joginder200109 Observer in Ethernet 08-05-2020 0 6	0	6
	cannot relaunch simulation if using analog waveform style by ViennaAudio Observer in Simulation and Verification 08-05-2020 0 2	0	2
	QDMA SRIOV kernel panic by TaekyungHeo Participant in Alveo™ Accelerator Cards 08-05-2020 0 1	0	1
	使用bootgen的split模式生成bin文件 by zhouchao_zhito Newbie in 综合讨论 08-05-2020 0 0	0	0
	CORDIC 6.0 SQRT - wrong results by axel.schmidt@htw-dresden.de Visitor in Xilinx IP Catalog 08-05-2020 0 0	0	0
	Deploying of resnet50 inference on Arm-cortex CPU of Xilinx Zynq-7000 SoC by afef-86 Observer in AI and Vitis AI 08-05-2020 0 0	0	0
	RFSoC ZCU216 CLK104 Evaluation Kit 160MHz VCXO by zoharyo67 Visitor in Versal and UltraScale Architecture™ 08-05-2020 0 1	0	1
	Vitis 2020.1 GCC problem by jburke@rosen-group.com Visitor in Embedded Development Tools 08-05-2020 0 2	0	2
	C Synthesis on Vitis HLS with systemC by Adri Visitor in High-Level Synthesis (HLS) 08-05-2020 0 3	0	3
	ZYNQ-7两片ID相同的芯片同时使用 by siwess Newbie in Other FPGA Architecture 08-05-2020 0 0	0	0
	Can start Artix config sequence by beandigital Scholar in FPGA Configuration 08-05-2020 0 0	0	0
	ISERDES3 configuration for 1:8 deserialization by patrick_1 Observer in Versal and UltraScale Architecture™ 08-05-2020 0 8	0	8
	How to use python on Xilinx Zynq-7000 SoC ZC702 Evaluation Kit by Gilmeer Visitor in Vitis Acceleration, SDAccel, SDSoC 08-05-2020 0 1	0	1
	VCU118 evaluation board IBERT FMC PLUS error by Yeo-Reum Visitor in Xilinx Evaluation Boards 08-05-2020 0 2	0	2
	Creating a VHDL testbench containing multiple sub-components by malavikask Newbie in Simulation and Verification 08-05-2020 0 2	0	2
	ZCU102 not working properly? by emincetin Observer in Xilinx Evaluation Boards 08-05-2020 0 5	0	5
	请问如何在上位机上读取xdma的usr_irq_req的值 by 2243242818@qq.com Newbie in 互连 08-05-2020 0 2	0	2
	vivado hls cosim error by viv Newbie in High-Level Synthesis (HLS) 08-05-2020 0 1	0	1
	Vivado complains that xlconcat input pins are connected to different type of pins by arotenst Explorer in Xilinx IP Catalog 08-05-2020 0 9	0	9
	The FPGA of VCU128-ES1 is burned by lastsecond Visitor in Xilinx Evaluation Boards 08-05-2020 0 3	0	3
	使用Vitis-AI不会生成.bit文件吗? by Zarkpx Newbie in Vitis, HLS, Alveo, ML以及其他软件应用 08-05-2020 0 0	0	0