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Petalinux 2019.1 "Failed to open PetaLinux lib: librdi_commonxillic.so: cannot open shared object file" error! by pierlum Voyager in Embedded Linux 10-21-2019 0 4	0	4
C++ confusion: hls::stream or ap_fifo when reading from a real FIFO? by benedetto73 Observer in High-Level Synthesis (HLS) 10-21-2019 0 1	0	1
Ethernet simulation takes > 1ms by dimitris78 Visitor in Ethernet 10-21-2019 0 4	0	4
MIPI DSI Transmitter Subsystem sync timing by jhallen Visitor in Video 10-21-2019 0 1	0	1
communication beween two fpga by sy5809358@gmail.com Participant in Xilinx Evaluation Boards 10-21-2019 0 1	0	1
can i boot android on ZCU104 by kiran1490 Observer in Xilinx Evaluation Boards 10-21-2019 0 1	0	1
Error when compiling in SDK by jaume Visitor in Embedded Development Tools 10-21-2019 0 2	0	2
The Future is Bright: Fortune’s Future 50 List Ranks Xilinx Tops in Semis! by xilinx-blog Xilinx Employee in Xilinx Xclusive Blog 10-21-2019 1 0	1	0
Unable to debug the data in ddr while using xsct tool while os running in zcu102 board by shivateja2207@gmail.com Visitor in Embedded Development Tools 10-21-2019 0 1	0	1
XMPU not raising SError exceptions with caches enabled by adiaz004 Visitor in Xilinx Evaluation Boards 10-21-2019 0 0	0	0
DDS Compiler Output by mdemirtas89 Visitor in AI Engine, DSP IP and Tools 10-21-2019 0 3	0	3
KC705 Power Problem by canberk_unal Visitor in Xilinx Evaluation Boards 10-21-2019 0 4	0	4
Synthesis Stuck at Running_Synth by hamzamuneer Visitor in Synthesis 10-21-2019 0 1	0	1
ZCU111 RFSOC ADC S-parameter file port naming convention by arve9066 Participant in Versal and UltraScale Architecture™ 10-21-2019 0 2	0	2
xapp398 by justin.powell@draeger.com Visitor in Memory Interfaces and NoC 10-21-2019 0 1	0	1
Petalinux ADI build fails by ajt Visitor in Embedded Linux 10-21-2019 0 1	0	1
DPU task scheduling or pin cores? by jiansheng@baidu.com Visitor in Machine Learning 10-21-2019 0 2	0	2
ZynqMP PetaLinux - USB ULPI 5V VBUS enable by tsillanp Adventurer in Embedded Linux 10-21-2019 0 1	0	1
zcu106 trd 2019.1: self-hosted package enabled causes kernel crash by kallensf Observer in Embedded Linux 10-21-2019 0 8	0	8
How to find the nets with the DONT_TOUCH attribute by kirito0816 Observer in Design Entry 10-21-2019 0 2	0	2
Debugging Zynq-7020 with Xilinx SDK + Segger JLink by whuang Visitor in Embedded Development Tools 10-21-2019 0 4	0	4
i tried to write the content of histogram in a file but this error is appeared :error:Second argument of write must have a constant value.... by duaa_basman@yahoo.com Newbie in FPGA Configuration 10-21-2019 0 1	0	1
Configuring PHYs in device tree by aaron_b1 Explorer in Embedded Linux 10-21-2019 0 10	0	10
ZynqMP USB Bare-Metal Driver: Sharing a solution to the problem that XUsbPsu_EpXferComplete() does not return the correct actual number of bytes transferred. by vvilly Visitor in Xilinx Evaluation Boards 10-21-2019 3 5	3	5
how to optimise long carry8 chain on vcu1525 by abdullahlokh Visitor in Timing Analysis 10-21-2019 0 1	0	1
Forcing vivado to use LAGUNA regs by drmerxius Visitor in Implementation 10-21-2019 0 8	0	8
Peta 2019.1 strips symbols from kernel modules when copying to rootfs by kallensf Observer in Embedded Linux 10-21-2019 0 2	0	2
10G Ethernet ZCU106 by tinghao780609 Observer in Xilinx Evaluation Boards 10-21-2019 0 1	0	1
Running AXI4 Stream through HLS block, trouble with C2H channel by benris Visitor in PCIe and CPM 10-21-2019 0 0	0	0
DSP Blocks by samah Newbie in Other FPGA Architecture 10-21-2019 0 6	0	6
Vivado 2019.1 IOBUF changes vs. 2018.7 or upgrade problems? by pyzahl Visitor in Implementation 10-21-2019 0 13	0	13
Unused or power-cycled VCCOs (7 Series) by johnhandwork Visitor in Other FPGA Architecture 10-21-2019 0 11	0	11
Aurora core by sail52 Visitor in Xilinx Evaluation Boards 10-21-2019 0 0	0	0
Vivado 2018.3 won't launch on Ubuntu 18.04: java.lang.reflect.InvocationTargetException by lematthias Observer in Installation and Licensing 10-21-2019 0 10	0	10
Kintex 7 by mubasheerahmed_12 Participant in Other FPGA Architecture 10-21-2019 0 3	0	3
How to view boolean logic optimized pre-synthesis netlist in Vivado 2019.1 by jdb2 Visitor in Simulation and Verification 10-21-2019 0 1	0	1
libmetal AMP Demo by tmonaghan84 Adventurer in OpenAMP 10-21-2019 0 3	0	3
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations by thilankathi Visitor in Design Entry 10-21-2019 0 4	0	4
QDMA Platform by madhukrishna_kaza Visitor in Alveo™ Accelerator Cards 10-21-2019 0 1	0	1
Open Camera Error for ZedBoard by overing1314 Newbie in Machine Learning 10-21-2019 0 0	0	0
Alveo U280 with Dell EMC PowerEDGE R7515 by viktor Newbie in Alveo™ Accelerator Cards 10-21-2019 0 3	0	3
How to open SDA tool with existing project by kathir_252525 Visitor in SDAccel 10-21-2019 0 0	0	0
SDSoC Platform from the command line by astromorgan Visitor in Vitis, SDAccel and SDSoC 10-21-2019 0 0	0	0
Xilinx Ila frequency 400khz by trivenianunag@gmail.com Observer in Xilinx Evaluation Boards 10-21-2019 0 1	0	1
Use 32 Bit Linux IBIS Model on 64 bit Linux ADS by devlikanova_333 Visitor in Other FPGA Architecture 10-21-2019 0 1	0	1
Provisioning ZynqMP from Uboot/Linux by tobibuhl Visitor in ACAP and SoC Boot and Configuration 10-21-2019 0 5	0	5
[DRC PLIDC-4] IDELAYCTRL IODELAYs with conflicting groups for same bank: Found IODELAY cells with different IODELAY group constraints for same I/O bank 35. by prasanna_18 Contributor in Memory Interfaces and NoC 10-21-2019 0 0	0	0
VCU118 QSPI Flash Die erase by rkvr Observer in Xilinx Evaluation Boards 10-21-2019 0 0	0	0
Fifo Generator and ARM CPU interface by cvasselin Visitor in Memory Interfaces and NoC 10-21-2019 0 0	0	0
Use Package Constant in Block Diagram by hkassir72 Participant in Design Entry 10-21-2019 0 3	0	3
AI’s Energy Problem (and what we have done about it) – Part 1 by gregmart Xilinx Employee in AI and Machine Learning Blog 10-21-2019 0 0	0	0
Unable to handle kernel paging request at virtual address b7ff9000 by apollo-micro Observer in Embedded Linux 10-21-2019 0 6	0	6
SDAccel Data transfer between Host to Device using XDMA by kathir_252525 Visitor in Alveo™ Accelerator Cards 10-21-2019 0 1	0	1
GTX CPLL occasionally not locking on powerup by curtiscolonero@copiousimaging.com Visitor in Serial Transceivers 10-21-2019 0 6	0	6
Questions about SDAccel Licenses for Alveo by xil_tour Explorer in Vitis, SDAccel and SDSoC 10-21-2019 0 0	0	0
decent error by lzhao Observer in Machine Learning 10-21-2019 0 6	0	6
AXI Stream fifo with different input/output data width size by sebo Explorer in Video 10-21-2019 0 7	0	7
Ethernet SGMII design for KCU 116 by najath_akram Visitor in Ethernet 10-21-2019 0 2	0	2
Error Place 30-640 by dkasmin Contributor in Xilinx IP Catalog 10-21-2019 0 3	0	3
Multi-Tile Sync : Adjusting NCO LO at run-time by dlee32 Participant in Versal and UltraScale Architecture™ 10-21-2019 0 3	0	3
platform data by jothiadithya Explorer in Embedded Linux 10-21-2019 0 4	0	4
Using IBERT for PS GTR SATA while running Linux OS by jchewpoc Observer in Serial Transceivers 10-21-2019 1 3	1	3
ERROR: unable to open xlnk by huadj1 Visitor in Vitis, SDAccel and SDSoC 10-21-2019 0 9	0	9
FPGA with two synchronous clock input by betontalpfa Explorer in Timing Analysis 10-21-2019 0 8	0	8
Transceivers Wizard on ZCU102 by emilie Participant in Serial Transceivers 10-21-2019 0 13	0	13
Long integer comparison in vivado hls by chandu_sathi Observer in High-Level Synthesis (HLS) 10-21-2019 0 2	0	2
Vivado HLS BRAM cant read back by jekot Visitor in High-Level Synthesis (HLS) 10-21-2019 0 1	0	1
scoped to ref xdc files not working on files inside IP by trehcir Observer in Timing Analysis 10-21-2019 0 0	0	0
FIFO full getting full at wrong time by a4speaker Explorer in Xilinx IP Catalog 10-21-2019 0 2	0	2
MicroBlaze Compiler by druehm92 Visitor in Processor System Design 10-21-2019 1 3	1	3
Zynq UltraScale+ LPDDR4 signal skew by blynskey_thinci Observer in Memory Interfaces and NoC 10-21-2019 0 2	0	2
PL Ethernet 1G by ttyler777 Observer in Embedded Linux 10-21-2019 0 1	0	1
hls_linear_algebra library errors by microlijun Visitor in High-Level Synthesis (HLS) 10-21-2019 0 1	0	1
Regarding Writing from HLS module to the DDR by fkhalili Adventurer in High-Level Synthesis (HLS) 10-21-2019 0 0	0	0
PS-PL communication monitoring from Linux (PS side) by sahebi.amin Observer in Embedded Linux 10-21-2019 1 2	1	2
xfOpenCV on custom SDSoC platforms - undefined reference to __libc_csu_init by astromorgan Visitor in Vitis, SDAccel and SDSoC 10-21-2019 0 1	0	1
Creating Custom IP and connecting it to a board component by gmims Newbie in Design Entry 10-21-2019 0 3	0	3
Secure boot of Zynq-7000 SoC by andreac_avnet Explorer in ACAP and SoC Boot and Configuration 10-21-2019 0 3	0	3
How to generate gram matrix Z=GG^H where G is a Rayleigh fading channel matrix? by mjuliza_1 Observer in High-Level Synthesis (HLS) 10-21-2019 0 6	0	6
Error: Subprogram <mmcm_count_calc> does not have a body when creating vhdl package. by cesar182 Adventurer in Synthesis 10-21-2019 0 0	0	0
Debug on ZCU106 Eval: "no supported debug core" by joe306 Explorer in Xilinx Evaluation Boards 10-21-2019 0 9	0	9
How many max MMCM's driven by single port ? by ssampath Voyager in Timing Analysis 10-21-2019 0 1	0	1
Bluetooth on zynqmp with sdio bus by vijaydhoki Contributor in Embedded Linux 10-21-2019 0 0	0	0
Ist it possible to verify RSA signature outside of the device? by svdmark Adventurer in General Technical Discussion 10-21-2019 0 0	0	0
Gmii-to-Rgmii driver by ian@lang Observer in Ethernet 10-21-2019 0 22	0	22
Incorrect setup/hold times in datasheet report by dbrent Visitor in Timing Analysis 10-21-2019 0 1	0	1
vivado2017.2配置v7415t时界面卡死，win7专业版64位中文 by songjn Visitor in 7 Series FPGA & 其他 FPGA 器件 10-21-2019 0 0	0	0
Build Image for ZCU104 Vivado 2018.2 in Linux (Error) by adelga16 Visitor in Xilinx Evaluation Boards 10-21-2019 0 6	0	6
Help setting IO Std for DDR4 Pins by joe306 Explorer in Memory Interfaces and NoC 10-21-2019 1 3	1	3
2 independent graphics on Mpsoc, is possible? by mrbietola Voyager in Embedded Linux 10-21-2019 0 0	0	0
AXI DMA stopped working after 7 hours of operation in xapp1305 + 1588 by timing@idt Observer in Embedded Linux 10-21-2019 0 1	0	1
Webpack 2019.1 installation by victor.avila-cobos Visitor in Installation and Licensing 10-21-2019 0 18	0	18
Output unstable in FPGA or whatsoever. Logics are correct by veteranbarneyzhu Visitor in FPGA Configuration 10-21-2019 0 4	0	4
GT transceiver wizard clocking by rajatrao Adventurer in Serial Transceivers 10-21-2019 0 6	0	6
Artix 7 GTP transceiver not received data by manb Participant in Serial Transceivers 10-21-2019 0 6	0	6
How to compare variable environment in u-boot? by sonminh Contributor in Embedded Linux 10-21-2019 0 9	0	9
System Synchronous data transmission by george_mrch Observer in Other FPGA Architecture 10-21-2019 0 3	0	3
Board needed for a brushless motor demo by victor.avila-cobos Visitor in Xilinx Evaluation Boards 10-21-2019 0 10	0	10
AXI_BRAM controller writes to four addresses by vgl94 Observer in Processor System Design 10-21-2019 0 3	0	3
microblaze with temac by esapla Visitor in Ethernet 10-21-2019 0 3	0	3
Bank 14 reconfiguration of VCCO, Artix 7 by gilessj Visitor in Other FPGA Architecture 10-21-2019 0 7	0	7
Why is uart0 blocking uart1 ? by halilkariyerhalil Newbie in OpenAMP 10-21-2019 0 0	0	0
One solution to error: "Failed to compile generated C file xsim.dir/ ... /xsim_1.c" by buckd Visitor in Simulation and Verification 10-21-2019 4 3	4	3
How to perform read and write to pl ddr by veekshitha Participant in Memory Interfaces and NoC 10-21-2019 0 5	0	5
DDR4 sequential write throughput by sandkumc663 Observer in Memory Interfaces and NoC 10-21-2019 0 4	0	4
Vivado-SDK-2018.2使用 by 1993833617@qq.com Adventurer in Vivado 10-21-2019 0 0	0	0
Spartan 7: can't adjust full range of IDELAYE2 for ISERDESE2 by linux-fanatic-777 Visitor in Other FPGA Architecture 10-21-2019 0 5	0	5
chipscope中采样后信号采样率 by xiao_bainet Observer in 其他设计工具问题 10-21-2019 0 1	0	1
Failed to build kernel(ip) by marcb123 Newbie in Vitis, SDAccel and SDSoC 10-21-2019 0 0	0	0
在SDsoc环境下，如何将硬件函数接口设置成任意精度数据 by whao Visitor in SDx 10-21-2019 0 3	0	3
AXI4-Stream FIFO packet count by qdeslandes Newbie in Processor System Design 10-21-2019 0 0	0	0
ZCU102 IBERT GTH Debug Core not working in example design. by tmindenh1 Observer in Serial Transceivers 10-21-2019 0 4	0	4
Automatic logging testbench signals - testbench_wave.do by luke_richardson Newbie in Simulation and Verification 10-21-2019 0 4	0	4
Vivado tool using LUT for inverting the clock, Is it fine for timing or there are any Xilinx primitives are exists for inverting the clk ? by ssampath Voyager in Synthesis 10-21-2019 0 1	0	1
Ultrascale MPSoc ZU11 LP-DMA safety requirement by chrbey Visitor in Versal and UltraScale Architecture™ 10-21-2019 0 2	0	2
ERROR: [Common 17-70] by philexqklip Visitor in Synthesis 10-21-2019 0 3	0	3
How to create a hybrid executable with python DNNDK API's by jbond1007 Observer in Machine Learning 10-21-2019 0 0	0	0
US+ 100G CMAC 2.6 on Alveo u200 board by pwz@semihalf.com Visitor in Ethernet 10-21-2019 0 2	0	2
dBFS calculation by linhtt Visitor in General Technical Discussion 10-21-2019 0 0	0	0
petalinux-build ERROR: Function failed: do_compile device tree file by krunal704 Observer in Xilinx Evaluation Boards 10-21-2019 0 7	0	7