Community Forums

506 Members Online 165K Discussions 48.2K Solutions

Community Activity

	Vivado2018接口固接lut优化不彻底 by nihao1234g Observer in Vivado 07-10-2020 0 10	0	10
	ERROR: [Place 30-487] after just changing the package (same number LUTs, BRAMs, DSPs, ...) by andre_schmidt Participant in Implementation 07-10-2020 0 4	0	4
	Frequency difference between RXUSRCLK and TXUSRCLK in GTP transceiver by daranda314 Visitor in Serial Transceivers 07-10-2020 0 0	0	0
	A7的GTP可以和K7的GTX通信吗 by 847508540@qq.com Observer in 其他FPGA器件架构 07-10-2020 0 0	0	0
	macb driver unable to generate target frequency: 25000000 by felven Adventurer in Embedded Linux 07-10-2020 0 3	0	3
	Zynq linux eth0 lost its ip addr by felven Adventurer in Embedded Linux 07-10-2020 0 0	0	0
	DSP48E1 simulaton in Ultrascale+ device by melkin Explorer in Simulation and Verification 07-10-2020 0 0	0	0
	AXI Quad SPI 3.2 transmit problem: infrequent garbage data and odd number of bits by bkuschak Contributor in Processor System Design and AXI 07-10-2020 0 0	0	0
	Tandem PCIe Tandem1/Tandem2 BIN Files Identical by aaron.bouillet Visitor in FPGA Configuration 07-10-2020 0 4	0	4
	UltraZed-EG Displayport and X11 No Screen Problem by mrberman87 Observer in Embedded Linux 07-10-2020 0 16	0	16
	does max_fanout result in more control sets? by melkin Explorer in Synthesis 07-10-2020 0 0	0	0
	Slave Detection in I2C Read by eldrick Contributor in Processor System Design and AXI 07-10-2020 0 0	0	0
	Clocking Wizard v6.0 Configuration Registers by kustinj Visitor in Other FPGA Architecture 07-10-2020 0 2	0	2
	Block RAM fall-back with Ultra RAM overutilization by HRZ Observer in High-Level Synthesis (HLS) 07-10-2020 0 0	0	0
	How to implement memset(), memcpy() to PL memory space by legendbb Voyager in Memory Interfaces and NoC 07-10-2020 0 0	0	0
	MPSoC - SD card not detected on Zynq UltraScale+ by cahitugur Observer in ACAP and SoC Boot and Configuration 07-10-2020 0 3	0	3
	TXOUTCLK driving RXUSRCLK with Buffer Bypassed enabled by daranda314 Visitor in Serial Transceivers 07-10-2020 0 9	0	9
	Vivado HLS compilation error when trying to rebuild an IP from the Vitis Vision Library by noah98 Newbie in High-Level Synthesis (HLS) 07-10-2020 0 0	0	0
	INtel CPU + Xilinx AI Acceleraror Interface by cdacabhi Observer in Alveo™ Accelerator Cards 07-10-2020 0 0	0	0
	Connect HLS to BRAM through AXI master interface by m.r.rohanipoor Contributor in High-Level Synthesis (HLS) 07-10-2020 0 1	0	1
	Tensorflow2 frozen graph does not work by drama Newbie in AI and Vitis AI 07-10-2020 0 0	0	0
	Failed to install docker image on Windows machine by drama Newbie in AI and Vitis AI 07-10-2020 0 2	0	2
	Vitis DSP48 latency ruins performance by kaustubhmhatre Observer in Vitis Acceleration, SDAccel, SDSoC 07-10-2020 0 1	0	1
	Linux Domain Not an Option After Upgrading to Vitis 2020.1 by jlanza3 Visitor in Embedded Development Tools 07-10-2020 0 0	0	0
	ug583 PCB Design Guide Acronym by AP_Spencer Visitor in Serial Transceivers 07-10-2020 0 0	0	0
	SDK 2019.1: MPSoC R5 lockstep baremetal in TCM: Debugger causes DAP status 0x30000021 failure on startup when code/data > 128K by dcattley Visitor in Embedded Development Tools 07-10-2020 0 6	0	6
	Can FSBL load App image into OCM without a DDR? by rayman Newbie in ACAP and SoC Boot and Configuration 07-10-2020 0 1	0	1
	Zynq7000 Multiboot Register reserved bits? by jdefields Explorer in ACAP and SoC Boot and Configuration 07-10-2020 0 1	0	1
	Sharing a quad between PCIe and Aurora by srdjan.opacic Adventurer in PCIe and CPM 07-10-2020 0 0	0	0
	JTAG Boot with ENC_ONLY and RSA_ENABLE set by seorasray Visitor in ACAP and SoC Boot and Configuration 07-10-2020 0 4	0	4