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XADC: continuous simultan sampling with changing sequence: timing? by thomasdon Explorer in 7 Series FPGAs 4 seconds ago 0 4	0	4
want to run the synthesis of c file in vivado HLS by ankittetarwal@123 Newbie in Vivado High-Level Synthesis (HLS) 35 seconds ago 0 1	0	1
SelectMAP on Kintex Ultrascale by pavel_47 Explorer in Configuration a minute ago 0 1	0	1
SDSoC Event Tracing Error by nessvan Contributor in SDSoC Environment and reVISION Stacks 10m ago 0 2	0	2
SDK new project error by ananth Newbie in Embedded Development Tools 11m ago 0 3	0	3
SDK and multiple devices loading and debugging by rebakker Observer in Embedded Development Tools 11m ago 0 4	0	4
FPGA RECOVERY FIRWARE LOADING by shijurkrishna Newbie in Configuration 14m ago 0 1	0	1
want to run the synthesis of c file in vivado HLS by hemangd Moderator in Synthesis 14m ago 0 0	0	0
MGTYAVTT current and noise requirements by sdunbar Newbie in Serial Transceivers 16m ago 0 3	0	3
How to fix that " Error downloading program to target" in SDK by skyfall133 Observer in Embedded Development Tools 20m ago 0 3	0	3
Not able to generate compiled tensorflow model output by durga_bhavani Visitor in Xilinx ML Suite 20m ago 0 0	0	0
请问哪里可以找到LINUX下的配置88E1512的驱动文件 by wandtdk Adventurer in UltraScale & UltraScale+ 架构 23m ago 0 0	0	0
QEMU doesn't work with petalinux 2018.2 by aic_y.suzuki Visitor in Embedded Development Tools 24m ago 0 3	0	3
Output jitter. Excluding PLL by ken_run Visitor in Virtex® Family FPGAs 25m ago 0 1	0	1
help about the phy(88E1512) by gnarahar Moderator in UltraScale Architecture™ 28m ago 0 0	0	0
help about the phy(88E1512) by wandtdk Adventurer in Embedded Processor System Design 28m ago 0 0	0	0
SelectMAP on Zynq-7000 devices by pavel_47 Explorer in Configuration 46m ago 0 4	0	4
Redeem the Vivado Tools License Voucher by durgesh_r Newbie in Installation and Licensing 50m ago 0 4	0	4
How to synchronize GTX transmitters across multiple FPGAs by dpachowicz Newbie in Serial Transceivers 51m ago 0 1	0	1
Issue with IP components with 2018.2 ? by colombini_luca Adventurer in Design Entry 55m ago 0 0	0	0
about XCZU3EG-1SFVC784I Power Sequence by wang_3130 Visitor in UltraScale Architecture™ an hour ago 0 5	0	5
memset() function in SDSoC Program (zcu102 board) crashes with "Bus error" message by koziotis Visitor in SDSoC Environment and reVISION Stacks an hour ago 0 2	0	2
Source processing failed by rashedkoutayni Visitor in Vivado High-Level Synthesis (HLS) an hour ago 0 1	0	1
Custom IP driver not present on BSP by brechat Observer in Embedded Development Tools an hour ago 0 3	0	3
Adding HLS OpenCV IP Core to Arty-Z7-20 HDMI In Demo Project by dcc3 Observer in Vivado High-Level Synthesis (HLS) 2 hours ago 0 1	0	1
XC7k325T DDR3 by yu_yang Visitor in 存储接口&视频 2 hours ago 0 7	0	7
zcu102 TRD 2018.2 的 HDMI init 失敗 by blake_ding Visitor in 存储接口&视频 2 hours ago 0 0	0	0
why latches are considered bad??? by hamzaali Observer in Implementation 2 hours ago 0 8	0	8
How to choose correct FPGA part or standard board ? by ssampath Explorer in General Technical Discussion 2 hours ago 0 6	0	6
Vivado 2016.4 detects production devices as ES1 devices by raja1 Explorer in Configuration 2 hours ago 0 7	0	7
FPGA RECOVERY FIRWARE LOADING by syedz Moderator in Implementation 2 hours ago 0 0	0	0
FMC VADJ by tobis Visitor in Evaluation Boards 2 hours ago 0 3	0	3
ZCU102 - Zynq UltraScale+ Devices Register - Control_Reg (I2C) Registers by chepner Visitor in Embedded Development Tools 2 hours ago 0 3	0	3
文件系统中添加库在petalinux-build -c rootfs阶段报错 by sdyang Visitor in 嵌入式软件开发 2 hours ago 0 0	0	0
Interface parameter bitwidth must be a multiple of 8 for AXI4 master port. Then how to use ap_uint<4> datatype? by akshayjrkp Observer in 7 Series FPGAs 2 hours ago 0 0	0	0
如何获取Minized适用的dts文件 by keep Visitor in 嵌入式软件开发 2 hours ago 0 0	0	0
Linux环境下，Vivado_HLS提示OpenCV未编译的问题 by dragon53567 Visitor in Vivado 2 hours ago 0 1	0	1
I need license by leekwangho Newbie in Installation and Licensing 2 hours ago 0 1	0	1
SD card by lukewllr1 Newbie in Embedded Linux 2 hours ago 0 1	0	1
Error while building Linux image with PetaLinux by herogian Participant in Embedded Linux 2 hours ago 0 2	0	2
Bootgen - BOOT.bin Image generation Issue by chepner Visitor in Embedded Boot and Configuration 2 hours ago 0 0	0	0
vivado和visual studio或者qt creator by ceelgao Visitor in Vivado 3 hours ago 0 1	0	1
RFADC PLL output clock not coming out by a4speaker Explorer in UltraScale Architecture™ 3 hours ago 0 2	0	2
CSI2-RX Subsystem IO PIns by ziladdev Contributor in Video 3 hours ago 0 5	0	5
HLS video library (hls::remap) by murad_qasaimeh Visitor in Vivado High-Level Synthesis (HLS) 3 hours ago 0 7	0	7
无法申请产品退回分析 by lulu_cheng Visitor in 综合讨论 3 hours ago 0 5	0	5
debug the driver of IP PCIE with DMA by yanghaofei@ni Visitor in PCI Express 3 hours ago 0 2	0	2
Is Post-Implementation Timing Simulation result important? by agary Observer in Simulation and Verification 3 hours ago 0 7	0	7
Vivado 2017.4 remote hosts by bsnajder_amp Visitor in Design Entry 3 hours ago 0 2	0	2
mark hdl record for debug by mariano_severi Adventurer in Simulation and Verification 3 hours ago 0 2	0	2
XADC dual adc data collecting by benaka Adventurer in 7 Series FPGAs 3 hours ago 0 7	0	7
Block Design Error by astrome Visitor in Synthesis 3 hours ago 0 4	0	4
Xilinx MIPI TX Timing parameters(THS-PREPARE,THS-ZERO) by jobincyriac Visitor in Video 3 hours ago 1 2	1	2
vivado2015.4中如何在Zynq 7045上例化LVDS或SERDES？ by caojunsitp Visitor in 嵌入式硬件开发 MPSoC & Zynq-7000 3 hours ago 0 1	0	1
ARTY Artix-7 Pmod SD and Pmod GPS Development by msujonathan Newbie in Evaluation Boards 3 hours ago 0 5	0	5
Registers removed by Synthesis by pavel_47 Explorer in Synthesis 3 hours ago 0 3	0	3
VCU-TRD : clock constraints by sebo Explorer in Video 3 hours ago 0 6	0	6
Enormous Vectors, limited I/O workarounds by dck140130 Visitor in Synthesis 3 hours ago 0 4	0	4
10/100 ethernet MAC in Zynq MSoC by suppamax Observer in Networking and Connectivity 4 hours ago 0 5	0	5
Can RTL code from VIVADO HLS be synthesized by SyopySdc DC? by xiazaixue Visitor in Vivado High-Level Synthesis (HLS) yesterday 0 2	0	2

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