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Your source for Xilinx announcements, customer success stories, industry trends and more.
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Xilinx products, tools, IP, boards, and solution news directly from our subject matter experts to you.
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Community forum for open source and community projects.
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About Our Community
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Latest announcements, new features, and usage.
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New to the Community? Get started by checking out our community guidelines and introduce yourself to the community.
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Discuss new Xilinx products, applications, and solutions. If you have a technical inquiry please search our community or browse our technical categories such as Programmable Devices or Embedded Solutions.
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Alveo™ and Boards
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Discuss the new Alveo™ portfolio.
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Discuss Xilinx evaluation boards, kits, FMC daughter-cards, and reference designs.
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Programmable Devices
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A board to discuss topics on Kintex UltraScale, Virtex UltraScale, Kintex UltraScale+, Virtex UltraScale+, Zynq UltraScale+ MPSoC, and Zynq UltraScale+ RFSoC including device architecture, clocking, SelectIO, signal integrity, packaging, power, data converters and related topics. This board excludes the Processor Subsystem (PS) and Embedded specific topics which are covered in the Embedded forums.
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A board to discuss topics on Artix™-7, Kintex™-7, Spartan™-7, Virtex®-7 FPGAs and Zynq-7000 SoCs including device architecture, clocking, SelectIO, signal integrity, packaging, power, and related topics. This board excludes the Processor Subsystem (PS) and Embedded specific topics which are covered in the Embedded forums.
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Discuss topics on Virtex-6, Virtex-5, Virtex-4, Virtex-II Pro, Virtex-II, Virtex/E/EM, and mature devices including device architecture, clocking, SelectIO, signal integrity, packaging, power, and related topics. This board excludes MicroBlaze based designs which are covered in the Embedded forums.
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Discuss topics on Spartan-6, Spartan-3A DSP, Spartan-3AN, Spartan-3A, Spartan-3E, Spartan-3, Spartan-IIE, Spartan-II, Spartan/XL, and mature devices. This board excludes MicroBlaze based designs which are covered in the Embedded forums.
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Discuss Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, iMPACT, and Vivado Device Programmer software related topics.
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Discuss transceiver and transceiver wizard related topics.
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Applications
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Discuss topics accelerating AI on DC and Cloud platforms with Xilinx ML Suite.
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Discuss topics accelerating AI on Edge and Embedded platforms with Xilinx Deephi DNNDK.
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Design Tools
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Discuss topics involving installation, licensing, updates, and operating system support for all products in the Vivado™ Design Suite and the ISE Design Suite™.
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Discuss topics involving HDL synthesis tools and practices, including Vivado™ Synthesis, XST™, 3rd party synthesis tools, HDL coding practices and tips.
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Discuss topics involving simulation and verification tools and flows, including XSIM and ISE Simulator™, 3rd party simulators, and formal verification.
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Discuss topics involving design implementation tools and practices, including Vivado™ Implementation, Translate, Map, Place and Route, SmartXplorer, and FPGA Editor.
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Discuss Xilinx tools for design entry and management, including Vivado™ IP Catalog, IP packager, Project Navigator™, Core Generator™, Schematic Entry, and other related topics.
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Discuss topics involving timing analysis including tools and best practices, including Timing closure and XDC Timing Analyzer™, TRACE™, Timing Constraints, and Speed Files.
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Discuss TCL usage in Vivado. Users are encouraged to share their scripting examples and questions.
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Discuss Vivado™ High-Level Synthesis and best practices for C, C++ and SystemC specifications to be directly targeted into Xilinx devices.
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Discuss the UltraFast Design Methodology, Design Methodology Checklist, RTL Coding styles, Baselining, Partial Reconfiguration and Design Preservation flows, design planning tools and flows.
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Discuss SDAccel™ development environment for OpenCL™, C, and C++ which enables application acceleration leveraging FPGAs.
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Discuss tools not covered by the other existing boards including Vivado Logic Analyzer, ChipScope Pro, Power Estimation tools, iMPACT, and others.
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Embedded Systems
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Discuss Processor system design for Zynq UltraScale+ MPSoC/RFSoC, Zynq-7000, MicroBlaze, and PicoBlaze. Includes both Processor Subsystem (PS) peripherals and Programable Logic (PL) IP Peripherals that are not covered by other boards such as UART, USB, SATA, DDR, GEM, AXI Ethernet, I2C, UART, etc. Additionaly includes the Vivado Processor Configuration Wizard (PCW) for Zynq-7000 and Zynq UltraScale+ SoC's.
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Discuss Embedded Software and Hardware development tools including SDK, Debugger Tools, XPS, updatemem, ELF Association.
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Discuss AXI Infrastructure specifc topics including AXI SmartConnect, AXI Interconnect, AXI-Stream, bridges, DMA cores, PS-PL AXI Interfaces, Custom AXI Peripherals, BFM and AXI Verification IP (VIP).
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Discuss board bring-up, boot and configuration topics for Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze based FPGA designs. Topics include secure and non-secure boot flow including programming the boot device (QSPI, JTAG, SD eMMC, NAND, NOR), bootrom, FSBL, loading of the bitstream, fallback/multi-boot, programming of eFUSEs and BBRAM.
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Discuss Embedded Linux topics for Xilinx FPGAs/SOCs including PetaLinux, meta-Xilinx Yocto layers, Xilinx Open Source Components and Commercial Linux from Xilinx Ecosystem vendors.
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Discuss SDSoC Development Environment and reVISION Stack related topics and issues.
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Discuss OpenAMP project for Zynq-7000, Zynq UltraScale+ MPSoC and MicroBlaze.
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Intellectual Property
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Discuss topics on PCI Express.
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Discuss Networking and connectivity IP cores including Ethernet, Aurora, JESD, CPRI, and related topics.
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Discuss MIG GUI,DDR4, QDRIV,DDR3,DDR2,DDRII, RLDRAM,QDR,QDRII, LPDDR2 and LPDDR3, MCB, HBM Controller, and related topics.
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Discuss System Generator, Model Composer, and Digital Signal Processing Ips such as Modulations, Filters, Transforms, Wireless (DPD, PC-CFR), Error Correction, and more.
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Discuss Video Processing and Connectivity IP – HDMI, DisplayPort, UHD-SDI, Video Processing Subsystem, VCU, and more.
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Discuss IP including Block Memory Generator, FIFO Generator, Distributed Memory Generator, and ECC.
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