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IP is locked by user，Recommendation：Unlock BD Cell for upgrade 如何消除IP锁定 by xudakang Visitor in Vivado 01-28-2021 0 0	0	0
Unable to reply to a post: post flooding detected by dschussheim Explorer in Welcome & Join 01-28-2021 0 7	0	7
ip核设计 by jisooismine Visitor in Vitis, HLS, Alveo, ML以及其他软件应用 01-28-2021 0 1	0	1
开发XILINX Virtex-5 的必备条件有哪些 by guorz Visitor in Xilinx评估板 01-28-2021 0 3	0	3
DP1.4 rxss receive YCbCr422 color format by furball Adventurer in Video and Audio 01-28-2021 0 18	0	18
System Generator block gui does not work by abbey_ Visitor in AI Engine, DSP IP and Tools 01-28-2021 0 2	0	2
HBM 随机地址读写性能 by heaventong Observer in Versal and UltraScale 架构 01-28-2021 0 2	0	2
Vivado 2019.2: export_simulation -export_source_files switch causes the -include switch to be ignored by rkuenzel Newbie in Simulation and Verification 01-28-2021 0 0	0	0
System Generator block error by abbey_ Visitor in AI Engine, DSP IP and Tools 01-28-2021 1 2	1	2
How to make PL-DDR accessible for Vitis (Vision) Kernels on ZCU104 by rbriegel Contributor in Vitis Acceleration, SDAccel, SDSoC 01-28-2021 0 8	0	8
struct declaration in kernel lead to sw_emu build failure by XilinxVivadoUbu Visitor in Vitis Acceleration, SDAccel, SDSoC 01-28-2021 0 1	0	1
HDMI output problem by rfrith Observer in Video and Audio 01-28-2021 0 0	0	0
How to use vivadoRuntime command,after the vivadoRuntime Script sourced which is taken from the thread "Saving Compile Time Series 4" by kishor_reddy Visitor in Vivado Debug and Power Estimation Tools 01-28-2021 0 0	0	0
eth1 NOK with U-Boot v2018.3, zynq-zc706, micrel KSZ9031 by ajk Contributor in Embedded Linux 01-28-2021 0 1	0	1
Web Installer: Could Not Connect to the Internet (2017.4 version) by CarlosAyy Visitor in Simulation and Verification 01-28-2021 0 4	0	4
XRT for Ubuntu 20.04 LTS by lbcom Visitor in Vitis Acceleration, SDAccel, SDSoC 01-28-2021 0 2	0	2
[DNNDK] DPU configuration mismatch for kernel xp0 on ultra96v2 by BruceChen Newbie in AI and Vitis AI 01-28-2021 0 0	0	0
PL与PS数据交互出错，如何查错？ by ywxiao Explorer in 嵌入式工具&软件开发 01-28-2021 0 1	0	1
QSGMII v3.4 MGTREFCLK issue by maxim_p Observer in Xilinx IP Catalog 01-28-2021 0 8	0	8
Image Enhancement 8.0 License for testing by andre_schmidt Participant in Xilinx IP Catalog 01-28-2021 0 0	0	0
Can ZCU208 RFSOC realize TIADC? by brucelone Visitor in Versal and UltraScale Architecture™ 01-28-2021 0 1	0	1
Understanding AXI DMA by szoshi Visitor in Processor System Design and AXI 01-28-2021 0 12	0	12
Clock Wizard v6.0中的Minimize Power在时钟网络结构上与default有什么区别？ by xudongdong Visitor in 其他IP应用 01-28-2021 0 1	0	1
Can't see /dev/ttyPS1 (second UART) after enabling FPGA Manager on MPSoC by sajaz Visitor in Embedded Linux 01-28-2021 0 0	0	0
click mezzanine board by Preeti20 Visitor in Xilinx Evaluation Boards 01-28-2021 0 0	0	0
petalinux 加载FPGA bit文件 by victor_tudou Visitor in 嵌入式硬件系统开发 01-28-2021 0 4	0	4
关于不同芯片之间的aurora通信链路问题 by kingwen Visitor in 其他IP应用 01-28-2021 0 8	0	8
关于在PYNQ-Z2板子上布署DPU以及其使用方式 by s1511215112 Visitor in 嵌入式硬件系统开发 01-28-2021 0 8	0	8
SPI register access using the Zync SOC and N25Q128 by Krishna Newbie in ACAP and SoC Boot and Configuration 01-28-2021 0 1	0	1
Install of ISE 14.7_VM on windows 10 Pro by darwineg Visitor in Installation and Licensing 01-28-2021 0 1	0	1