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PCIe sys_clk port selection about 7 series FPGA by zhikai Observer in 7 Series FPGAs 13m ago 0 0	0	0
How can I ensure lower DSP resource utilization comparing with pure HDL coder model? by luckfyzhang Observer in DSP IP and Tools 21m ago 0 3	0	3
Xilinx XPower Analyzer Confidence Level by dayana42200 Contributor in Design Tools - Others 33m ago 0 21	0	21
Axi crossbar outstanding by orit Visitor in UltraScale Architecture™ 44m ago 0 0	0	0
PetaLinux 2018.1 Install Fails on Debian Stretch by cdsteinkuehler Visitor in Embedded Linux 49m ago 7 4	7	4
Camera Link Receiver by murali@1996 Visitor in UltraScale Architecture™ 50m ago 0 5	0	5
petalinux-build 生成系统文件时出现error by pidan0121 Newbie in General Technical Discussion 55m ago 0 0	0	0
[DRC 23-20] Rule violation (INBB-3) Black Box Instances by nitzan_shitrit Visitor in 7 Series FPGAs an hour ago 0 0	0	0
How to burned xc3s50an flash with power-of-2 mode by bill.xu Visitor in 7 Series FPGA & 其他 FPGA 器件 an hour ago 0 0	0	0
XDMA driver AR 65444 installed correctly but no devices were recognized by dlfc Observer in PCI Express an hour ago 0 4	0	4
Vivado 2016.3 how to know if routing utilization close to full? by kaza Newbie in Implementation 2 hours ago 0 2	0	2
Spi eeprom ip core for spartan6 by sameer1234 Newbie in Spartan® Family FPGAs 2 hours ago 0 2	0	2
read checksum from the configuration memory device in vivado with tcl command by murali@1996 Visitor in Vivado TCL Community 2 hours ago 0 0	0	0
Vivado keeps restarting sythesis by beandigital Voyager in Synthesis 2 hours ago 0 2	0	2
how to write input/output delay with clock mux by leileier Newbie in Timing Analysis 2 hours ago 0 2	0	2
Installing Vivado 2018.2 corrupts the Vivado 2018.1 Installation by verilog@all Newbie in Installation and Licensing 2 hours ago 0 0	0	0
SV_VHDL mix language simulation issue by verilog_bee Visitor in Simulation and Verification 3 hours ago 0 2	0	2
Unusual Problem with ISE Project Navigator by onatop94 Newbie in Configuration 3 hours ago 0 0	0	0
关于ps端efuse误烧写问题 by baronwang13146688 Adventurer in 嵌入式硬件开发 MPSoC & Zynq-7000 3 hours ago 0 3	0	3
GTX & GTH comma alignment word by abbu_2390 Contributor in Serial Transceivers 3 hours ago 0 0	0	0
FIR filter design by abitofmaya Observer in DSP IP and Tools 3 hours ago 0 6	0	6
Looking for some help/education about getting desired parallelism: by andrewsi Visitor in Vivado High-Level Synthesis (HLS) 3 hours ago 0 0	0	0
Adding comments to COE file by gauravbhatia Visitor in General Technical Discussion 4 hours ago 0 5	0	5
INOUT wrapper synthesized wrong? by panikplauze Visitor in Synthesis 4 hours ago 0 10	0	10
Detailed Thermal package model of VU13P by yarras Newbie in Virtex® Family FPGAs 4 hours ago 0 6	0	6
Why worst negative slack is reduced after implementation? by linofex Visitor in Implementation 4 hours ago 0 4	0	4
Synthesis never ends by panayiotis95 Newbie in Synthesis 4 hours ago 0 3	0	3
Forcing value in simulation vs. driving in testbench by mc76 Newbie in Simulation and Verification 4 hours ago 0 1	0	1
Why a long stall happens during data read? by mathmaxsean Explorer in SDAccel 5 hours ago 0 4	0	4
PetaLinux 2018.3 installation failure (caused by required packages) by watari Scholar in Embedded Development Tools 5 hours ago 0 2	0	2
XC7VX690T-2FFG1158I焊接上测量短路 by lingye1994 Visitor in 7 Series FPGA & 其他 FPGA 器件 5 hours ago 0 7	0	7
HLS loop_tripcount影响综合结果 by yaoyinqi Observer in 其他设计工具问题 5 hours ago 0 6	0	6
VC709 公版設計資料急需 by andy_hsieh Newbie in 7 Series FPGA & 其他 FPGA 器件 6 hours ago 0 1	0	1
programming Flash in ZC702 development board by tchin123 Explorer in 7 Series FPGAs 6 hours ago 0 3	0	3
Invalid DAP ack (=0) when executing ps7_post_config by uyeshiro Adventurer in Embedded Development Tools 6 hours ago 0 7	0	7
SDAccel运行vadd时src里没有host.cpp文件，无法进行Debug调试 by gaoge Newbie in SDx 6 hours ago 0 3	0	3
INVALID DAP ACK VALUE 7 ERROR by theertharamesha Adventurer in Configuration 6 hours ago 0 7	0	7
C2H Streaming XDMA Linux Driver Broken by dwd_pete Visitor in PCI Express 6 hours ago 2 32	2	32
How to align the phase of the output clock which is generated by MMCM to input clock. by swseo83 Visitor in Timing Analysis 6 hours ago 0 1	0	1
How does Zynq PS I2C IXR_DATA interrupt work? by wtneo@leica Adventurer in Embedded Processor System Design 7 hours ago 0 1	0	1
GTYE4 Channel DRP Register Reference by jim@dryv.io Newbie in Serial Transceivers 7 hours ago 0 0	0	0
Problems with petalinux and baremetal uses customized DMA by infinityfju Visitor in Embedded Linux 7 hours ago 0 2	0	2
Why Source Clock Path is too long? by swseo83 Visitor in Timing Analysis 7 hours ago 0 6	0	6
ug903 by dariush84 Contributor in Timing Analysis 7 hours ago 3 10	3	10
Artix 7 XADC Auxilliary Channel Pins by jdabbs003 Visitor in 7 Series FPGAs 9 hours ago 0 0	0	0
Kernel panic by gastonmelo1980 Observer in Embedded Linux 9 hours ago 0 0	0	0
Internal Exceptions on Vivado 2017.1 Windows 7 by etemprano Visitor in Vivado TCL Community 9 hours ago 0 0	0	0
vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design by benaka Adventurer in Implementation 9 hours ago 0 0	0	0
Very bad Vivado 2018.3 Automatic Incremental Implementation results by jpn123 Visitor in Implementation 10 hours ago 0 2	0	2
SPI extension via GPIO by anthonygclark Newbie in 7 Series FPGAs 12 hours ago 0 1	0	1
CDC: Read registers from slow clock domain in fast clock domain (intermittent fast clock) by losttime77 Visitor in Timing Analysis 12 hours ago 0 10	0	10
合肥开住宿费发票 by linbojuea Newbie in Open Source and Community Projects Discussion 13 hours ago 0 0	0	0
兰州开发票@▌☏溦ィ訁▌【159⇋1415⇋8529】联系⒬⒬【599⇋987⇋798】-.哪里有开▐░▒▓▐░▒▓▐░▒▓▐░▒▓▐░▒▓▐░▒▓▐░▒▓▐░▒▓广告、酒店住宿、餐饮、机械设备、服务、建筑、租赁、建材、劳务、办公用品、咨询、材料、工程款、会议. , 合作共赢 by linbojuea Newbie in General Technical Discussion 13 hours ago 0 0	0	0
xsim crashes by jkellam Newbie in Simulation and Verification 14 hours ago 0 2	0	2
[filemgmt 20-2001] Source scanning failed; all the source files are shown under Non-module Files folder by musthafavakeri Adventurer in Design Entry 14 hours ago 0 2	0	2
Vivado HLS RTL/Cosimulation Fail by sajjad_b Visitor in Simulation and Verification 14 hours ago 0 2	0	2
Missing files in ISE post route simulation by mountain902 Visitor in Simulation and Verification 14 hours ago 0 1	0	1
../standalone_v5_1/src/config.make": no such file or directory by mspalpsahan Observer in Embedded Processor System Design 15 hours ago 0 1	0	1
Data transfer from PL to PS MIO peripherals by user@moduleus Contributor in Embedded Processor System Design 15 hours ago 0 1	0	1
Vivado 2018.3 Synthesis on AMD CPUs by brendar-li Visitor in Synthesis 15 hours ago 0 6	0	6

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