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关于xilinx的IP axi_interconnect RTL1.7 挂死后复位也不起作用的问题

问题1,在slave口写的数据个数超过len的个数后,再发起第二个burst(拉起AWVALID),master口读完第一个burst数据后,axi interconnecte会挂死(m00口收不到valid信号),确认一下这个问题。

问题2,如下图所示,上电复位后,总线没有卡死的情况下产生第二次复位,释放后逻辑正常,由于写的数据大于burst个数,总线卡死(m00口收不到valid信号),在第三次复位释放后,s00口正常发送数据,但在m00口收不到valid信号?ss

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Xilinx Employee
Xilinx Employee

回复: 关于xilinx的IP axi_interconnect RTL1.7 挂死后复位也不起作用的问题

问题一的情况已经违反axi4总线协议,应该修改掉。

问题二的reset现象,你还需要复位所有master和slave接口,包括它们所连接的master和slave。所有reset要有同时reset时间,reset持续时间要大于16个时钟周期,如果时钟频率不同,选择最慢的时钟计算。具体要求,参考PG059里面的“Resets”那一章节。

 

Resets


Each of the SI, MI and Crossbar aclk is accompanied by an aresetn input, which must be
synchronized to the corresponding aclk. (This version of the AXI Interconnect core does
not internally resynchronize any aresetn inputs.)


All AXI Interconnect Infrastructure cores deassert all valid and ready outputs shortly
after aresetn is sampled active, and for the duration of the aresetn pulse.


IMPORTANT: Each of the SI and MI must be put into the reset state at some time during the reset cycle
of the Crossbar, and vise-versa, for every occurrence of reset. None of the AXI Interconnect cores
support partial resetting. That is, whenever one interface is reset, all interfaces must be reset, and the
resets must overlap. It is not necessary for multiple aresetn inputs to be deasserted during the same
clock cycle.

 

IMPORTANT: All cores connected to the AXI Interconnect core, or to any AXI Infrastructure core
described in this document, must have their connected AXI interface put into the reset state (aresetn
outputs deasserted) at some time during the reset cycle of the AXI Interconnect core (must overlap), for
every occurrence of reset. None of the AXI Interconnect cores support resetting one end of an AXI
interface connection without the other, in either direction. It is not necessary for the aresetn input of
the connected core to be deasserted during the same clock cycle as the AXI Interconnect core.


RECOMMENDED: As a general design guideline, Xilinx recommends asserting system aresetn signals
for a minimum of 16 clock cycles (of the slowest aresetn), as that is known to satisfy the preceding
reset requirements.