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Visitor yu_yang
Visitor
264 次查看

XC7k325T DDR3

HELLO,

When I debugged DDR3 on k7, I always reported an error:

The component ins_ddr3_control/ins_ddr3_sdram/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out belongs to a RPM (its structure is printed below) with 11 instances in the design, and there are only 8 suitable sites to place such RPMs in the device. 

 

why?

 

How to solve?

 

0 项奖励
5 条回复
Xilinx Employee
Xilinx Employee
254 次查看

回复: XC7k325T DDR3

Did you assign the memory interface pinout within the MIG IP?
0 项奖励
Visitor yu_yang
Visitor
234 次查看

回复: XC7k325T DDR3

this is my ucf document .

 

 

##################################################################################################
##
##  Xilinx, Inc. 2010            www.xilinx.com
##  周三 十月 17 09:51:28 2018
##  Generated by MIG Version 1.9
##  
##################################################################################################
##  File name :       ddr3_sdram1.ucf
##  Details :     Constraints file
##                    FPGA Family:       KINTEX7
##                    FPGA Part:         XC7K325T-FFG900
##                    Speedgrade:        -2
##                    Design Entry:      VERILOG
##                    Frequency:         533.333 MHz
##                    Time Period:       1875 ps
##################################################################################################

##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->SODIMMs->MT16KSF51264HZ-1G4
## Data Width: 64
## Time Period: 1875
## Data Mask: 1
##################################################################################################

#NET "sys_clk_i" TNM_NET = TNM_sys_clk;
#TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 1.875 ns;
          
#NET "clk_ref_i" TNM_NET = TNM_clk_ref;
#TIMESPEC "TS_clk_ref" = PERIOD "TNM_clk_ref" 5 ns ;
          
############## NET - IOSTANDARD ##################

NET   "ddr3_dq[0]"                             LOC = "AD3"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L1N_T0_34
NET   "ddr3_dq[1]"                             LOC = "AC2"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L2P_T0_34
NET   "ddr3_dq[2]"                             LOC = "AC1"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L2N_T0_34
NET   "ddr3_dq[3]"                             LOC = "AC5"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L4P_T0_34
NET   "ddr3_dq[4]"                             LOC = "AC4"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L4N_T0_34
NET   "ddr3_dq[5]"                             LOC = "AD6"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L5P_T0_34
NET   "ddr3_dq[6]"                             LOC = "AE6"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L5N_T0_34
NET   "ddr3_dq[7]"                             LOC = "AC7"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L6P_T0_34
NET   "ddr3_dq[8]"                             LOC = "AF2"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L7N_T1_34
NET   "ddr3_dq[9]"                             LOC = "AE1"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L8P_T1_34
NET   "ddr3_dq[10]"                            LOC = "AF1"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L8N_T1_34
NET   "ddr3_dq[11]"                            LOC = "AE4"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L10P_T1_34
NET   "ddr3_dq[12]"                            LOC = "AE3"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L10N_T1_34
NET   "ddr3_dq[13]"                            LOC = "AE5"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L11P_T1_SRCC_34
NET   "ddr3_dq[14]"                            LOC = "AF5"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L11N_T1_SRCC_34
NET   "ddr3_dq[15]"                            LOC = "AF6"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L12P_T1_MRCC_34
NET   "ddr3_dq[16]"                            LOC = "AH4"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L13P_T2_MRCC_34
NET   "ddr3_dq[17]"                            LOC = "AJ4"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L13N_T2_MRCC_34
NET   "ddr3_dq[18]"                            LOC = "AH6"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L14P_T2_SRCC_34
NET   "ddr3_dq[19]"                            LOC = "AH5"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L14N_T2_SRCC_34
NET   "ddr3_dq[20]"                            LOC = "AJ2"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L16N_T2_34
NET   "ddr3_dq[21]"                            LOC = "AJ1"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L17P_T2_34
NET   "ddr3_dq[22]"                            LOC = "AK1"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L17N_T2_34
NET   "ddr3_dq[23]"                            LOC = "AJ3"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L18P_T2_34
NET   "ddr3_dq[24]"                            LOC = "AF7"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L20P_T3_34
NET   "ddr3_dq[25]"                            LOC = "AG7"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L20N_T3_34
NET   "ddr3_dq[26]"                            LOC = "AJ6"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L22P_T3_34
NET   "ddr3_dq[27]"                            LOC = "AK6"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L22N_T3_34
NET   "ddr3_dq[28]"                            LOC = "AJ8"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L23P_T3_34
NET   "ddr3_dq[29]"                            LOC = "AK8"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L23N_T3_34
NET   "ddr3_dq[30]"                            LOC = "AK5"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L24P_T3_34
NET   "ddr3_dq[31]"                            LOC = "AK4"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L24N_T3_34
NET   "ddr3_dq[32]"                            LOC = "AK15"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L1N_T0_32
NET   "ddr3_dq[33]"                            LOC = "AG15"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L2P_T0_32
NET   "ddr3_dq[34]"                            LOC = "AH15"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L2N_T0_32
NET   "ddr3_dq[35]"                            LOC = "AF15"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L4P_T0_32
NET   "ddr3_dq[36]"                            LOC = "AG14"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L4N_T0_32
NET   "ddr3_dq[37]"                            LOC = "AH17"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L5P_T0_32
NET   "ddr3_dq[38]"                            LOC = "AJ17"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L5N_T0_32
NET   "ddr3_dq[39]"                            LOC = "AE16"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L6P_T0_32
NET   "ddr3_dq[40]"                            LOC = "AK19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L7N_T1_32
NET   "ddr3_dq[41]"                            LOC = "AG19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L8P_T1_32
NET   "ddr3_dq[42]"                            LOC = "AH19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L8N_T1_32
NET   "ddr3_dq[43]"                            LOC = "AD19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L10P_T1_32
NET   "ddr3_dq[44]"                            LOC = "AE19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L10N_T1_32
NET   "ddr3_dq[45]"                            LOC = "AF18"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L11P_T1_SRCC_32
NET   "ddr3_dq[46]"                            LOC = "AG18"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L11N_T1_SRCC_32
NET   "ddr3_dq[47]"                            LOC = "AF17"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L12P_T1_MRCC_32
NET   "ddr3_dq[48]"                            LOC = "AD18"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L13P_T2_MRCC_32
NET   "ddr3_dq[49]"                            LOC = "AE18"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L13N_T2_MRCC_32
NET   "ddr3_dq[50]"                            LOC = "AD17"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L14P_T2_SRCC_32
NET   "ddr3_dq[51]"                            LOC = "AD16"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L14N_T2_SRCC_32
NET   "ddr3_dq[52]"                            LOC = "AB18"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L16N_T2_32
NET   "ddr3_dq[53]"                            LOC = "AB19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L17P_T2_32
NET   "ddr3_dq[54]"                            LOC = "AC19"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L17N_T2_32
NET   "ddr3_dq[55]"                            LOC = "AB17"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L18P_T2_32
NET   "ddr3_dq[56]"                            LOC = "AA15"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L20P_T3_32
NET   "ddr3_dq[57]"                            LOC = "AB15"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L20N_T3_32
NET   "ddr3_dq[58]"                            LOC = "AC14"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L22P_T3_32
NET   "ddr3_dq[59]"                            LOC = "AD14"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L22N_T3_32
NET   "ddr3_dq[60]"                            LOC = "AA17"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L23P_T3_32
NET   "ddr3_dq[61]"                            LOC = "AA16"    |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L23N_T3_32
NET   "ddr3_dq[62]"                            LOC = "Y16"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L24P_T3_32
NET   "ddr3_dq[63]"                            LOC = "Y15"     |   IOSTANDARD = SSTL15_T_DCI         |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L24N_T3_32
NET   "ddr3_addr[14]"                          LOC = "AB9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L3P_T0_DQS_33
NET   "ddr3_addr[13]"                          LOC = "AC9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L3N_T0_DQS_33
NET   "ddr3_addr[12]"                          LOC = "Y11"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L4P_T0_33
NET   "ddr3_addr[11]"                          LOC = "Y10"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L4N_T0_33
NET   "ddr3_addr[10]"                          LOC = "AA11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L5P_T0_33
NET   "ddr3_addr[9]"                           LOC = "AA10"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L5N_T0_33
NET   "ddr3_addr[8]"                           LOC = "AA13"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L6P_T0_33
NET   "ddr3_addr[7]"                           LOC = "AB13"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L6N_T0_VREF_33
NET   "ddr3_addr[6]"                           LOC = "AB10"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L7P_T1_33
NET   "ddr3_addr[5]"                           LOC = "AC10"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L7N_T1_33
NET   "ddr3_addr[4]"                           LOC = "AD8"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L8P_T1_33
NET   "ddr3_addr[3]"                           LOC = "AE8"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L8N_T1_33
NET   "ddr3_addr[2]"                           LOC = "AC12"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L9P_T1_DQS_33
NET   "ddr3_addr[1]"                           LOC = "AC11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L9N_T1_DQS_33
NET   "ddr3_addr[0]"                           LOC = "AD9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L10P_T1_33
NET   "ddr3_ba[2]"                             LOC = "AE9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L10N_T1_33
NET   "ddr3_ba[1]"                             LOC = "AE11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L11P_T1_SRCC_33
NET   "ddr3_ba[0]"                             LOC = "AF11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L11N_T1_SRCC_33
NET   "ddr3_ras_n"                             LOC = "AD12"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L12P_T1_MRCC_33
NET   "ddr3_cas_n"                             LOC = "AD11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L12N_T1_MRCC_33
NET   "ddr3_we_n"                              LOC = "AJ9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L15P_T2_DQS_33
NET   "ddr3_reset_n"                           LOC = "AG5"     |   IOSTANDARD = LVCMOS15             |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L12N_T1_MRCC_34
NET   "ddr3_cke[0]"                            LOC = "AH9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L16N_T2_33
NET   "ddr3_cke[1]"                            LOC = "AK11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L17P_T2_33
NET   "ddr3_odt[0]"                            LOC = "AK10"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L17N_T2_33
NET   "ddr3_odt[1]"                            LOC = "AH11"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L18P_T2_33
NET   "ddr3_cs_n[0]"                           LOC = "AK9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L15N_T2_DQS_33
NET   "ddr3_cs_n[1]"                           LOC = "AG9"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L16P_T2_33
NET   "ddr3_dm[0]"                             LOC = "AD4"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L1P_T0_34
NET   "ddr3_dm[1]"                             LOC = "AF3"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L7P_T1_34
NET   "ddr3_dm[2]"                             LOC = "AH2"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L16P_T2_34
NET   "ddr3_dm[3]"                             LOC = "AF8"     |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L19P_T3_34
NET   "ddr3_dm[4]"                             LOC = "AK16"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L1P_T0_32
NET   "ddr3_dm[5]"                             LOC = "AJ19"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L7P_T1_32
NET   "ddr3_dm[6]"                             LOC = "AA18"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L16P_T2_32
NET   "ddr3_dm[7]"                             LOC = "AE15"    |   IOSTANDARD = SSTL15               |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L19P_T3_32
NET   "ddr3_dqs_p[0]"                          LOC = "AD2"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L3P_T0_DQS_34
NET   "ddr3_dqs_n[0]"                          LOC = "AD1"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L3N_T0_DQS_34
NET   "ddr3_dqs_p[1]"                          LOC = "AG4"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L9P_T1_DQS_34
NET   "ddr3_dqs_n[1]"                          LOC = "AG3"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L9N_T1_DQS_34
NET   "ddr3_dqs_p[2]"                          LOC = "AG2"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L15P_T2_DQS_34
NET   "ddr3_dqs_n[2]"                          LOC = "AH1"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L15N_T2_DQS_34
NET   "ddr3_dqs_p[3]"                          LOC = "AH7"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L21P_T3_DQS_34
NET   "ddr3_dqs_n[3]"                          LOC = "AJ7"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L21N_T3_DQS_34
NET   "ddr3_dqs_p[4]"                          LOC = "AH16"    |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L3P_T0_DQS_32
NET   "ddr3_dqs_n[4]"                          LOC = "AJ16"    |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L3N_T0_DQS_32
NET   "ddr3_dqs_p[5]"                          LOC = "AJ18"    |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L9P_T1_DQS_32
NET   "ddr3_dqs_n[5]"                          LOC = "AK18"    |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L9N_T1_DQS_32
NET   "ddr3_dqs_p[6]"                          LOC = "Y19"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L15P_T2_DQS_32
NET   "ddr3_dqs_n[6]"                          LOC = "Y18"     |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L15N_T2_DQS_32
NET   "ddr3_dqs_p[7]"                          LOC = "AC16"    |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L21P_T3_DQS_32
NET   "ddr3_dqs_n[7]"                          LOC = "AC15"    |   IOSTANDARD = DIFF_SSTL15_T_DCI    |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L21N_T3_DQS_32
NET   "ddr3_ck_p[0]"                           LOC = "AA12"    |   IOSTANDARD = DIFF_SSTL15          |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L1P_T0_33
NET   "ddr3_ck_n[0]"                           LOC = "AB12"    |   IOSTANDARD = DIFF_SSTL15          |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L1N_T0_33
NET   "ddr3_ck_p[1]"                           LOC = "AA8"     |   IOSTANDARD = DIFF_SSTL15          |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L2P_T0_33
NET   "ddr3_ck_n[1]"                           LOC = "AB8"     |   IOSTANDARD = DIFF_SSTL15          |     VCCAUX_IO = NORMAL      |     SLEW = FAST        ; # Pad function: IO_L2N_T0_33



INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y3;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y2;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y1;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y0;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y8;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y3;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y2;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y1;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y0;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y8;



INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y3;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y2;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y1;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y0;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y8;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y3;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y2;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y1;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y0;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y11;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y10;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y9;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y8;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y0;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y2;

INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y0;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y2;


INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y43;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y31;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y19;
INST "*/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y143;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y131;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y119;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y107;

INST "u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1;
INST "u_ddr3_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y1;


NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 1875 ps;
TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;
          

INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;
         

 

 

 

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Xilinx Employee
Xilinx Employee
123 次查看

回复: XC7k325T DDR3

Did you choose "new design" in the pin assignment page? Was this ucf file generated by MIG IP? Have you modified or assign some pin allocation after MIG IP was generated?

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Visitor yu_yang
Visitor
96 次查看

回复: XC7k325T DDR3

yes, I choose "new design" in the pin assignment page,and the ucf file is  generated by MIG IP;

 I have modified or assign some pin allocation after MIG IP was generated,but the error has always been there.

 

 

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Xilinx Employee
Xilinx Employee
89 次查看

回复: XC7k325T DDR3

If you modified the pin allocation after MIG IP was generated, you have to reopen MIG IP and choose "verify pinout and update design".

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