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Observer
Observer
551 次查看
注册日期: ‎08-27-2018

IO有频率要求时,如何选择没有HP bank的器件

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Hi Xilinx

我们在选择Zynq器件时,出于成本考虑,准备选择一些低端器件,但有些器件没有HP bank。请问我们怎么确认,HR bank是否能够满足我们的IO的速度要求?设计余量应该留多少?

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Xilinx Employee
Xilinx Employee
501 次查看
注册日期: ‎06-02-2017

@xuyangfirst ,

如Borisq所示,实际可以达到的速度不仅与我们器件有关,还与其他因素有关,所以最理想的是使用我们的IBIS模型进行仿真。但如果仿真有苦难的话可以参考DS181的这个表格

 

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Xilinx Employee
Xilinx Employee
547 次查看
注册日期: ‎06-02-2017

@xuyangfirst 你好,

具体的设计需求是什么,IO上跑什么电平标准?

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Xilinx Employee
Xilinx Employee
519 次查看
注册日期: ‎08-08-2007

hi @xuyangfirst 

 

我们提供的IO的仿真模型,可以通过IBIS仿真来评估性能。

 

谢谢

Boris

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Xilinx Employee
Xilinx Employee
502 次查看
注册日期: ‎06-02-2017

@xuyangfirst ,

如Borisq所示,实际可以达到的速度不仅与我们器件有关,还与其他因素有关,所以最理想的是使用我们的IBIS模型进行仿真。但如果仿真有苦难的话可以参考DS181的这个表格

 

-------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------------------------------------------------------------------------------------------------

在原帖中查看解决方案

lvds_selectio.JPG