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Visitor qianbin1992
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注册日期: ‎03-17-2015

iodelay的tap延迟问题

调用Virtex-6的iodelay,工作在FIXED模式下,数据输入来自FPGA内部,当参数REFCLK_FREQUENCY与实际输入的参考时钟频率不相等时,通过modelsim后仿真发现, 延迟的tap值只与参数REFCLK_FREQUENCY有关,与实际输入的参考时钟频率无关。我想问的是,iodelay的每一个tap的延迟时间由什么决定?iodelay的内部详细结构是什么?希望详细解答,谢谢!

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回复: iodelay的tap延迟问题

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回复: iodelay的tap延迟问题

Hi  @qianbin1992,

 

Please go through the following link:

http://www.xilinx.com/support/documentation/application_notes/xapp707.pdf

 

Thanks,
Arpan

 

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Thanks,
Arpan
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