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Visitor zxue
Visitor
171 次查看
注册日期: ‎07-26-2017

verilog always模块

比如这样几条语句:

always@( a ) begin

   if( b == 0 ) begin

   ...

   end

   ...

end

在这个模块中,只要信号a变化,就会执行a模块,是这样吧。我想问的是,在这个IF判断语句中,判断的是哪个时刻的b,是在a变化前,还是a变化后,还是在a变化的同时判断b?如果是在a变化的时刻判断b是否为0,那么如果a和b是同时变化的,比如在a变化的同时,b从1变成了0,那么这种情况下,到底会把b判断成什么,是否执行if里的语句?新手小白求好心人回答~

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2 条回复2
Moderator
Moderator
156 次查看
注册日期: ‎05-23-2018

回复: verilog always模块

Hi, @zxue 

这种写法一般会综合为组合逻辑。在你的假设中,会把b判断为0,进入到if条件下的语句中。具体情况自己 可以仿真看一下。

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Scholar drjohnsmith
Scholar
151 次查看
注册日期: ‎07-09-2009

回复: verilog always模块

The always will only be executed if a is true,
so first off , you have a latch,

second as b is not in the sensetity list, changes on b will not be seen unless a is also true.

third , you will get difference between simulation and synthesis.

Basicaly bad design,

If you learning, suggest you try system verilog or VHDL , which both have better gamma checking,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>