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Contributor
Contributor
450 次查看
注册日期: ‎10-16-2018

关于cpll和qpll 多输出

用k7 FPGA gtx实现sdi接口时,需要rx_usrclk 和它的2 分频和4分频时钟,cpll qpll 可以像pll一样配置多个不同分频时钟么??

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Observer jack.lv
Observer
401 次查看
注册日期: ‎09-11-2018

回复: 关于cpll和qpll 多输出

是同时需要吗?

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Xilinx Employee
Xilinx Employee
379 次查看
注册日期: ‎06-02-2017

回复: 关于cpll和qpll 多输出

Hi @yongkangbi

能把你的要求说具体一些吗,“需要rx_usrclk 和它的2 分频和4分频时钟”是指你的用户逻辑中需要这两个分频时钟吗?如果是的,我们IP一般会把rx_usrclk作为usrclk输出给用户逻辑,在用户逻辑中使用一个MMCM就能产生你需要的这两路时钟了。 

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