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Visitor s_divyam1590
Visitor
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Registered: ‎12-07-2018

Architecture_FPGA

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Hi,

I have a strong confusion regarding how DRAM for LUT
is different from BRAM.

Help!!!

 

WBR,
Divyam

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Scholar u4223374
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Registered: ‎04-26-2015

Re: Architecture_FPGA

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I think that you may be confused; none of the on-chip RAM (LUT RAM, BRAM, or URAM) is DRAM-based. As far as I know, this is because DRAM requires a substantially different production process to the main FPGA fabric, so it's not practical to build both on one chip.

LUT RAM is RAM built from the FPGA LUTs. Not all LUTs can do this (about 1/4 - 1/3 seems to be normal). For those that can, each LUT can store up to 64 bits of data, and the LUTs within a slice can be combined in various ways to yield up to four read ports. LUT RAM is useful because it's very fast - it's scattered across the chip (other RAM types have their own area, so data has to be transferred to/from that area) and it can be read without needing a clock input.

BRAM (block RAM) is an enhanced RAM that drops the general-purpose nature of LUT RAM (ie you can't use it as LUTs), but adds some useful memory-specific features. In particular, because it's dedicated memory it stores far more data (the smallest amount you can use is 18Kb), it's got built-in FIFO support, and built-in error correction. It can have up to two ports, each of which is totally independent - they can have different clocks, different widths, etc). BRAM does require a clock, and every operation takes at least one clock cycle to complete - you cannot provide an address and get the data in the same cycle.

URAM (Ultra RAM) is a new feature in some of the big UltraScale+ chips. It's even more a dedicated RAM - only a single port (see below), and no FIFO support, but a single URAM module stores 288Kb. The big UltraScale+ chips can store over 100Mb of data. While URAM only has one port, it acts like it has two - the single port can do two read/write operations in a single clock cycle. However, unlike BRAM you can't use two separate clocks. URAM is also unable to accept user-defined values at power-on. BRAM can have its initial data stored in the bitstream, but URAM always starts filled with zeros.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Re: Architecture_FPGA

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Hi @s_divyam1590,

DRAM : Dynamic random Access Memory :  Read and write memory, but needs to be regularly refreshed during which you can't access the cells being refreshed.

 BRAM : Sram built into the FPGA.

 

Regards,

Deepak D N

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Visitor s_divyam1590
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Registered: ‎12-07-2018

Re: Architecture_FPGA

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Is there any document or can
u brief me on how data flows within various components of a CLB?

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Architecture_FPGA

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I think that you may be confused; none of the on-chip RAM (LUT RAM, BRAM, or URAM) is DRAM-based. As far as I know, this is because DRAM requires a substantially different production process to the main FPGA fabric, so it's not practical to build both on one chip.

LUT RAM is RAM built from the FPGA LUTs. Not all LUTs can do this (about 1/4 - 1/3 seems to be normal). For those that can, each LUT can store up to 64 bits of data, and the LUTs within a slice can be combined in various ways to yield up to four read ports. LUT RAM is useful because it's very fast - it's scattered across the chip (other RAM types have their own area, so data has to be transferred to/from that area) and it can be read without needing a clock input.

BRAM (block RAM) is an enhanced RAM that drops the general-purpose nature of LUT RAM (ie you can't use it as LUTs), but adds some useful memory-specific features. In particular, because it's dedicated memory it stores far more data (the smallest amount you can use is 18Kb), it's got built-in FIFO support, and built-in error correction. It can have up to two ports, each of which is totally independent - they can have different clocks, different widths, etc). BRAM does require a clock, and every operation takes at least one clock cycle to complete - you cannot provide an address and get the data in the same cycle.

URAM (Ultra RAM) is a new feature in some of the big UltraScale+ chips. It's even more a dedicated RAM - only a single port (see below), and no FIFO support, but a single URAM module stores 288Kb. The big UltraScale+ chips can store over 100Mb of data. While URAM only has one port, it acts like it has two - the single port can do two read/write operations in a single clock cycle. However, unlike BRAM you can't use two separate clocks. URAM is also unable to accept user-defined values at power-on. BRAM can have its initial data stored in the bitstream, but URAM always starts filled with zeros.

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Visitor s_divyam1590
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Registered: ‎12-07-2018

Re: Architecture_FPGA

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Thanks for the info, that satisfies well enough.
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Historian
Historian
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Registered: ‎01-23-2009

Re: Architecture_FPGA

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Just to throw in a sometimes confusing point...

Sometimes people refer to SelectRAM, otherwise known as "Distributed RAM" as DRAM (with the D for distributed). This leads to all kinds of confusion since DRAM mean "Dynamic RAM" to most people.

I suspect that this original question came from the misnaming of Distributed RAM as DRAM...

Avrum

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