UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer prakashdrj
Observer
7,924 Views
Registered: ‎07-12-2016

CDR of 7 Series GTX

Jump to solution
The clock and data recovery (CDR) unit in the GTX receiver can receive lines rates that are up to ±1250 ppm away from the nominal bit rate.
 
What if protocol has +300 to -5300 ppm?
 
Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
8,477 Views
Registered: ‎07-31-2012

Re: CDR of 7 Series GTX

Jump to solution
Hi the UG lists only the characterized value. You can characterize it at your end and decide on a value but we would not be able to support it. the only Characterized values as said are given in AR's, UG's or Datasheets.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
16 Replies
Xilinx Employee
Xilinx Employee
7,911 Views
Registered: ‎08-01-2008

Re: CDR of 7 Series GTX

Jump to solution

check this ARs

 

http://www.xilinx.com/support/answers/51884.html

 

PPM is an inaccuracy of certain components (quartz crystal in case of clock generator) in a circuit which leads to generation of a signal with inaccurate period. PPM does not break the periodicity of a signal. As its name states, PPM is a long term effect which denotes the inaccuracy in the bit period over a million clock cycles. PPM is additive or subtractive in nature.

Frequency-PPM-effect

Onlyif cumulative effect of jitter or PPM in TX CLK becomes more than half of RX CLK then there would be errors due to over/under sampling.

An example below shows how ongoing variations in incoming data stream can affect the sampling of data. This same example will be considered to resolve the issues as we progress further.

Variations-Data-Sampling-Frequency

RX CLK(FD) is frequency locked during frequency detection. As the incoming data stream is being sampled on FD, as depicted in the red box, a single bit is getting sampled twice. This occurs because of the variations in the incoming data bit stream. 

To encounter these variations in frequency of TX CLK, the second function of CDR, Phase alignment comes in picture. This  readjusts RX CLK edges.

 

PPM should be in within the specified limit of device vendor

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Observer prakashdrj
Observer
7,905 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

Hello @balkris,

 

I understood the concept, but if protocol has ppm in range of +300 to -5300 ppm then is there any changes in wrapper generated parameters? like RXCDR_CFG? because there is not any value of  RXCDR_CFG for +300 to -5300 ppm.

 

Thanks,

Prakash

0 Kudos
Xilinx Employee
Xilinx Employee
7,903 Views
Registered: ‎08-01-2008

Re: CDR of 7 Series GTX

Jump to solution
check the values given here
http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf
this is one related ARs
http://www.xilinx.com/support/answers/62616.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Observer prakashdrj
Observer
7,898 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

hello @balkris,

 

I have gone through it multiple times but not found any perfect information regarding values of RXCRD_CFG in case of +300 to -5300 ppm.

 

For your reference, SATA's setting for RXCRD_CFG which is generated by wrapper is also not listed in UG746.

 

//For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010

 

So can you explain me how can you people derive that valuations?

 

Regards,

Prakash

0 Kudos
Xilinx Employee
Xilinx Employee
7,887 Views
Registered: ‎08-01-2008

Re: CDR of 7 Series GTX

Jump to solution

These value suggested by silicon team and use need to use as it is as mention in UG

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
tt.png
0 Kudos
Moderator
Moderator
7,884 Views
Registered: ‎02-16-2010

Re: CDR of 7 Series GTX

Jump to solution
Which protocol has the range +300 to -5300 ppm?
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
7,882 Views
Registered: ‎07-31-2012

Re: CDR of 7 Series GTX

Jump to solution

Hi Prakash,

 

 

For what protocol are you looking to use the CDR_CFG for? Most of the supported protocols for the CDR are either mentioned in the Product Guide, through Answer Records or through the protocol selection in the GUI(where the CDR value can be checked in the GT files). These are the only protocols for which we officially support for the CDR.

 

Here is one AR which points the recommended CDR values - http://xkb/Pages/51/51884.aspx

 

I assume the CDR cannot support PPM of -5300 but have to cross-check on this. Will get back.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Observer prakashdrj
Observer
7,876 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

Hello @athandr,

 

Custom protocol like PCIe & SATA.

 

You can see the PCI_Express_Base_Specification_V20, where they have given base ppm of +/-300 and SSC of down spread of 0 to 5000 ppm. ultimately ppm in range of +300 to -5300 ppm.

 

SATA also has the range +350 to -5350 ppm.

 

Regards,

Prakash

0 Kudos
Xilinx Employee
Xilinx Employee
7,873 Views
Registered: ‎08-01-2008

Re: CDR of 7 Series GTX

Jump to solution
check this ARs
http://www.xilinx.com/support/answers/51369.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Observer prakashdrj
Observer
6,789 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

hey @balkris,

 

Same is applicable to GTX too?

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
6,784 Views
Registered: ‎08-01-2008

Re: CDR of 7 Series GTX

Jump to solution
I think no here i am point ARs for PPM ranges for some protocol .

let me check if i will found out for GTX
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Xilinx Employee
Xilinx Employee
6,784 Views
Registered: ‎08-01-2008

Re: CDR of 7 Series GTX

Jump to solution
check this ARs
http://www.xilinx.com/support/answers/53364.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Observer prakashdrj
Observer
6,783 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

@balkris,

 

That is exactly what I am asking, if SATA has custom valuation of RXCDR_CFG which UG not listed. Is there any way to obtain the parameter by ourselves?

0 Kudos
Observer prakashdrj
Observer
6,758 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

@athandr,

 

Hey do you have any update?

0 Kudos
Xilinx Employee
Xilinx Employee
8,478 Views
Registered: ‎07-31-2012

Re: CDR of 7 Series GTX

Jump to solution
Hi the UG lists only the characterized value. You can characterize it at your end and decide on a value but we would not be able to support it. the only Characterized values as said are given in AR's, UG's or Datasheets.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Observer prakashdrj
Observer
6,534 Views
Registered: ‎07-12-2016

Re: CDR of 7 Series GTX

Jump to solution

@athandr,

 

How we can characterize it at our end?

 

If you people not provide the support then something else method or procedure is there to do so.

 

Can you enlighten us?

 

Regards,

Prakash

0 Kudos