UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,042 Views
Registered: ‎12-30-2018

How to interface of ADC12D1800 with VC707 board with maximum efficiency?

I am trying to use Analog to Digital converter (ADC12D1800) with Virtex-7 board .I have achieved 710Mhz stable frequency with VC707 but ADC12D1800 have output data rate of 1.8 GSPS (12-bits sample).

How should I approach this???Need to acquire maximum number of samples.

Problem statement: I want to use ADC with 1.8GSPS and doesn’t have much higher clock frequency of VC707 board. Please guide.

Thanks in advance.

Regards,

Mufasir Fida Qureshi

0 Kudos
23 Replies
Highlighted
Moderator
Moderator
984 Views
Registered: ‎04-18-2011

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

I've not looked at the data sheet for this ADC very closely

Its got a parallel lvds interface, that seems to run at either the full sample rate or half the sample rate ddr. 

What is the data rate of the digital data?

I suspect the data is changing too fast for the iserdes to sample it. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
933 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Data rate is also 1.2 GBPS(15-bit sample in parallel containing 12-bits of data out).Ref Page 35 paragraph 4 and 5.

Datasheet is attached. 

 

 

0 Kudos
Mentor hgleamon1
Mentor
930 Views
Registered: ‎11-14-2011

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

The output data is produced at the rate it is sampled, ref:

6.1.3.2 Output Data Rate

The data is produced at the output at the same rate it is sampled at the input. The minimum recommended input clock rate for this device is fCLK(MIN); see Section 4.13. However, it is possible to operate the device in 1:2 Demux Mode and capture data from just one 12-bit bus, e.g. just DI (or DId) although both DI and DId are fully operational. This will decimate the data by two and effectively halve the data rate.

What is your sampling frequency?

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
911 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

I have achieved maximum 710MHz clock using VC707 board which will be the sampling clock for ADC12D1800 and that will allow me to acquire Maximum 710MSPS of data. But I want to achieve more data sample per second. How can I do that?

And how much maximum number of sample I can acquire from ADC12D1800 using VC 707 board???This is what I am trying to find out…..

Please guide.

0 Kudos
Mentor hgleamon1
Mentor
904 Views
Registered: ‎11-14-2011

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

The datasheet states that the output frequency is directly related to the sample frequency. So, if you want to simply increase the output data frequency you will have to increase the sample frequency.

I haven't studied and understood the different modes (DES, demux or non-demux) but this is it at it's simplest. Higher frequency in, higher frequency out.

What is the frequency of signal that you are trying to sample?

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
899 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

That’s right.

I want to receive 1575.42MHz GPS signal using ADC12D1800 and VC 707 board. How should I do???

Maximum clock frequency I achieved from VC 707 board is 710 MHz.

0 Kudos
Scholar drjohnsmith
Scholar
889 Views
Registered: ‎07-09-2009

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

I'd  look at using the iserdes blocks of the IO, and probably double data rate

 

plenty of app notes around on both

0 Kudos
Mentor hgleamon1
Mentor
888 Views
Registered: ‎11-14-2011

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

The ADC datasheet recommends using a clock synthesiser device such as the LMX2531LQ to provide the sample clock.

I had a quick look at the V7 datasheet and it suggests you could get a data rate of between 1250 and 1600 Mb/s for DDR LVDS data, depending on your speed grade and IO Bank Type.

I am afraid, however, that this is well outside my own design experience and capability, so I can't really advise you any further other than to read through the V7 design guides.

----------
"That which we must learn to do, we learn by doing." - Aristotle
884 Views
Registered: ‎06-21-2017

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

If you are trying to sample a signal, you need to sample at least twice the frequency of the signal.  This is the Nyquist/Shannon sampling theorem.  Practically speaking, if you want to process a signal, you should sample at 2.5 times the signal frequency or more.  I doubt that you could process this with a typical FPGA. 

Since you are going to need an antenna and a low noise amplifier, add a mixer and filter to your RF path and downconvert to a more reasonable frequency.  I haven't looked at the specs, but have you looked at the RFSoCs?

888 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Ok.

Thanks for your timely response to my problem.

I will go through V7 design guides.Please just Refer me to the document and page  from where your got this("it suggests you could get a data rate of between 1250 and 1600 Mb/s for DDR LVDS data, depending on your speed grade and IO Bank Type.").That will be appreciated.

 

0 Kudos
Mentor hgleamon1
Mentor
884 Views
Registered: ‎11-14-2011

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

DS183 page 15. UG471 has interesting information, too.

I think @bruce_karaffa has provided some better advice, though.

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
Participant nuelle85
Participant
857 Views
Registered: ‎04-27-2016

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

@mufasir_qureshi

I think you should start with the reference design of TI
They implemented it with a Virtex 4 and also offer FPGA design files.

http://www.ti.com/tool/ADC12D1800RFRB

838 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Ok.Thanks.

 

0 Kudos
Historian
Historian
797 Views
Registered: ‎01-23-2009

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

OK. Lets start with the first thing.

You cannot generate the ADC clock from the FPGA. Period.

Even if you could get a frequency that was high enough for the sampling rate you want, the quality of the clock generated by the FPGA is nowhere near good enough for driving an ADC - particularly an ADC with this high a sampling rate. The quality of an ADC's samples is very tightly tied to the quality of the clock - even the tiniest bit of jitter will have significant effect on the precision of the ADC. So give up on this - its just not going to work.

The clock for the ADC must come directly from a very high quality clock generation chip - an crystal oscillator or VCXO or something similar. No other solution is going to give you anything reasonable.

The FPGA only needs the DCLK and the and the DATA. The ADC12D1800 has several output modes, including modes where data is sent at 1/4 the sampling rate of the ADC. So if you are sampling at 1800Msps, your data rate is 450Mbps/pin, which is more than reasonable to capture in the FPGA - if done correctly, you might even be able to capture it statically.

But be warned - this interface will have to be done just right - you will have to ensure that the each interface (the Q and the I interfaces) are in different I/O banks, with the DCLK of the interface on a clock capable pair and the 22 differential D pairs associated with each clock on 22 of the 23 remaining differential inputs available on that bank. Anything else, and capturing this interface is going to be pretty much impossible. And even done just right, the timing is going to be very tight and you will need to use the correct clocking scheme and input capture style.

But, again, sourcing the clock for the ADC from the FPGA is just not viable.

Avrum

779 Views
Registered: ‎06-21-2017

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

As @drjohnsmith pointed out in a private message, the Nyquist sampling theorem requires us to sample at twice the bandwidth of the signal, not it's frequency.  This requires tight filtering on the signal or you can't separate the signal of interest from all of the aliased noise, but it's an interesting possibility.  I haven't looked, but for something as common as GPS, I wouldn't be surprised if there were some appropriate filters out there.  It looks like I owe him a kudos.

692 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Thanks,

I will get back to you after going through app notes.

0 Kudos
691 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Thanks for your suggestions. Appreciated.

 

0 Kudos
683 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Sorry but haven't looked at the RFSoCs but I will look into it.Actually i got VC707 only for now. Thanks for your valuable response.
0 Kudos
679 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Ok.

I am looking into it.

0 Kudos
676 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Got your point.Thanks for guidance.

I am looking into clocking modules likes TSW4806 which i got for now.

And will also study deeply proposed approaches and suggested material from all.

I got your approach and will get back to you after working on it.And will contact you if i got any question or confusion.

But thanks again to all for valuable guidance.

0 Kudos
377 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

I explored LMX2531LQ (553MHz to 3132MHz) and this is helpful for me. And also read about Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit but it seems it will not solve my problem.

Basically, I am working on Spectrum sensing and using ADC and VC 707 board with clock frequency of  250MHz achieved Band width of 125MHz.Now I am trying to increase my band width up to 1 GHz but considering my working and discussion with forum community I can say that with VC707 I can achieve Band width of only 355MHz.

What my understanding is that if I can increase my clock frequency it will also increases my Band width range. Am I right???

How can I increase receiving band width????What are your suggestion about it??? Hopefully you got what I am trying to do….

Please guide.

Thanks

0 Kudos
366 Views
Registered: ‎12-30-2018

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

I explored LMX2531LQ (553MHz to 3132MHz) and this is helpful for me. And also read about Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit but it seems it will not solve my problem.

Basically, I am working on Spectrum sensing and using ADC and VC 707 board with clock frequency of  250MHz achieved Band width of 125MHz.Now I am trying to increase my band width up to 1 GHz but considering my working and discussion with forum community I can say that with VC707 I can achieve Band width of only 355MHz.

What my understanding is that if I can increase my clock frequency it will also increases my Band width range. Am I right???

How can I increase receiving band width????What are your suggestion about it??? Hopefully you got what I am trying to do….

Please guide. Which FPGA will be best suitable for my requirement.?????

Thanks

0 Kudos
Mentor hgleamon1
Mentor
326 Views
Registered: ‎11-14-2011

Re: How to interface of ADC12D1800 with VC707 board with maximum efficiency?

Did you look at the example that used the Virtex 4? Is this not good enough for your needs?

Surely if TI have a reference design with a V4 you can achieve at least as good performance (and better, I imagine) with a V7 .. ? 

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos