03-20-2017 06:41 AM
In my system, dsp can't start programe rightly. FPGA have some input pins connect with DSP's pins.
If FPGA configuration is done, reset DSP can work well.
I want to know, during configuration of FPGA, io pins is high-impedance?
None, pullup, pulldown, keeper, which status should be choose? I choose none. I think the others is fit for output pins.
If FPGA pins is not high impedance, DSP maybe can't read flash rom rightly.
03-20-2017 07:52 AM
Need to know what your fpga is as different ones have different options, some selected by a pin.
you also need to ensure the dsp are held in reset till the voltages are stable on the fpga and dsp,
03-20-2017 10:55 AM
03-21-2017 06:04 AM
03-21-2017 06:24 AM
Status of IO pins during configuration depends on PUDC_B (Pull-Up During Configuration Bar) pin of 7 Series devices.
Active-Low PUDC_B input enables internal pull-up resistors on the SelectIO pins after power-up and during
7 Series FPGAs Configuration, UG470 (v1.11) September 27, 2016
03-23-2017 06:08 PM