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Is io pins high-impedance during configration?

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Observer
Posts: 15
Registered: ‎05-27-2016

Is io pins high-impedance during configration?

  In my system, dsp can't start programe rightly. FPGA have some input pins connect with DSP's pins.

 

  If FPGA configuration is done, reset DSP can work well.

 

  I want to know, during configuration of FPGA, io pins is high-impedance?

 

  None, pullup, pulldown, keeper, which status should be choose? I choose none. I think the others is fit for output pins.

 

  If FPGA pins is not high impedance, DSP maybe can't read flash rom rightly. 

   

Scholar
Posts: 1,849
Registered: ‎07-09-2009

Re: Is io pins high-impedance during configration?

Need to know what your fpga is  as different ones have different options, some selected by a pin.

 

you also need to ensure the dsp are held in reset till the voltages are stable on the fpga and dsp, 

Moderator
Posts: 5,297
Registered: ‎08-01-2008

Re: Is io pins high-impedance during configration?

General purpose IO's are tristate until configured by the bitstream (from power on reset to DONE).



There is a weak pullup that may be enabled on all IO before DONE is asserted controlled by a dedicated pin.



The dual purpose IO (used both for configuration, and later may be used as IO) are whatever the configuration mode needs them to be, until DONE, then they are defined by the design's bitstream.
Thanks and Regards
Balkrishan
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Observer
Posts: 15
Registered: ‎05-27-2016

Re: Is io pins high-impedance during configration?

FPGA: K7, SPI*4 flash , there is about 33 senconds in configration process.
Now after config_done pin turn to 1 from 0, reset DSP , the system work well.

I want to know, are IO pins high impedance during configration?

Yes, it are general purpose io pins connect between DSP and FPGA.
Visitor
Posts: 11
Registered: ‎06-17-2009

Re: Is io pins high-impedance during configration?

Status of IO pins during configuration depends on PUDC_B (Pull-Up During Configuration Bar) pin of 7 Series devices.

 

Active-Low PUDC_B input enables internal pull-up resistors on the SelectIO pins after power-up and during

configuration.

  • When PUDC_B is Low, internal pull-up resistors are enabled on each SelectIO pin.
  • When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin.

 

Reference:

7 Series FPGAs Configuration, UG470 (v1.11) September 27, 2016

(https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf)

 

 

 

 

 

Observer
Posts: 15
Registered: ‎05-27-2016

Re: Is io pins high-impedance during configration?

I set PUDC_B pin low.
When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. What does this mean? high impedance?
Visitor
Posts: 11
Registered: ‎06-17-2009

Re: Is io pins high-impedance during configration?

When PUDC_B is Low ->  all IO pins are pulled-up internally during configuration.

When PUDC_B is High -> all IO pins are 3-State during configuration.

Observer
Posts: 15
Registered: ‎05-27-2016

回复: Is io pins high-impedance during configration?

3-State is high impedance?
Moderator
Moderator
Posts: 1,298
Registered: ‎01-15-2008

回复: Is io pins high-impedance during configration?

yes, check the following link 

https://en.wikipedia.org/wiki/Three-state_logic

Observer
Posts: 15
Registered: ‎05-27-2016

回复: Is io pins high-impedance during configration?

1 PUDC_B pin only set non-dedicated configration pins. All io pins ? Are you sure? If this pin set all io pins, when you choose ""None, pullup, pulldown, keeper"" in io planning function, which will work?
2. For BSDL compliance, PUDC_B should be 0(ug470). PUDC_B is connected to gnd in all examples.

I will try.