UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor jukidav
Visitor
162 Views
Registered: ‎10-04-2013

Issue with Xilinx-7 series SERDES output

I am trying to simulate Xilinx-7 series SERDES. The SEREDES is configured as SDR 8 bit mode, single CE.The clkDiv, clk,Enable and data are generated as in attached figure. As per documentation data is expected on Q8. But I am getting it on Q2. rest is high for more than two clkDiv cycles. I am getting the following pattern at o/p:

Q2,Q1,Q8,Q7,...Q3.

Is anybody comeacross this simulation findings, kindly help to clarify what is the mistake.

 

Jayaraj

SERDES_OUTPUT.png
0 Kudos
2 Replies
Community Manager
Community Manager
85 Views
Registered: ‎08-08-2007

Re: Issue with Xilinx-7 series SERDES output

Hi @jukidav

 

When you simulate you should be able to see a signal on the ISERDES called the clkdiv_int and the word aligned of the serial data is determined by this clock.

For a simulation previously I had drawn up the alignment, the Q follows the clkdiv_int alignment not the clkdiv. This would be the same in HW

ISERDES.png

 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Visitor jukidav
Visitor
62 Views
Registered: ‎10-04-2013

Re: Issue with Xilinx-7 series SERDES output

Thank you for the reply. However when I simulate Xilinx-7 series SERDES, I could not able to see clkdiv_int signal. Kindly let me know which application note I need to refer for this. I am referring UG471.

 

Regards,

Jayaraj

0 Kudos