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Participant vapostolov
Participant
5,908 Views
Registered: ‎08-06-2013

Not able to disable input termination on BLVDS input

Using Vivado 2014.2 and xc7a200t device, I have instantiated IOBUFDS_INTERMDISABLE bidirectional BLVDS buffer in my design to drive a backplane.

This is a typical multipoint BLVDS configuration with backplane termination at both ends of the bus. Because of this, I need to disable the BLVDS buffer input termination. My buffer instantiation is:

 

 

PAD_COMMS_BUF : IOBUFDS_INTERMDISABLE
generic map (
DIFF_TERM => "FALSE", -- Differential Termination (TRUE/FALSE)
IBUF_LOW_PWR => "TRUE", -- Low Power - TRUE, High Performance = FALSE
IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
SLEW => "SLOW", -- Specify the output slew rate
USE_IBUFDISABLE => "TRUE") -- Use IBUFDISABLE function, "TRUE" or "FALSE"
port map (
O => commsUartRx, -- Buffer p-side output
IO => PAD_COMMS_P, -- Diff_p inout (connect directly to top-level port)
IOB => PAD_COMMS_N, -- Diff_n inout (connect directly to top-level port)
I => commsUartTx, -- Buffer input
IBUFDISABLE => commsInputEnable, -- Input disable input, low=disable
INTERMDISABLE => commsTerminationEnable, -- Input termination disable input
T => commsTristateEn -- 3-state enable input, high=input, low=output
);

Just to be sure I also have in my xdc file:

 

 

set_property DIFF_TERM FALSE [get_ports PAD_COMMS_P]
set_property DIFF_TERM FALSE [get_ports PAD_COMMS_N]

After the design is implemented, I checked the termination property in Vivado Tcl Console:

 

 

get_property DIFF_TERM [get_ports PAD_COMMS_P]
0
get_property DIFF_TERM [get_ports PAD_COMMS_N]
0

I also checked PAD_COMMS_BUF "Cell Properties" and verified the "DIFF_TERM" is not checked.

 

Unfortunately when I test the design, the in-build BLVDS input termination appears to be active.

I have disconnected the two backplane termination resistors and with one board transmitting in the rack, I see 760mV signal differential swing (non terminated bus).

When I insert a second board with BLVDS buffer configured as an input, the differential voltage swing drops to 420mV, which I believe is caused by the input internal termination.

The communications between the boards work as expected. Adding more receiver boards in the rack continue to squash the differential voltage as more input terminations are added to the bus.

 

Changing the INTERMDISABLE buffer control signal level doesn't make a difference.

 

Any clue why the input termination still appears to be there?

 

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10 Replies
Xilinx Employee
Xilinx Employee
5,895 Views
Registered: ‎08-01-2008

Re: Not able to disable input termination on BLVDS input

Check selectIO guide

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Participant vapostolov
Participant
5,883 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

Hi Balkrishan,

 

Thank you for trying to help. I sure read ug471 and a bunch of other Xilinx documentation (including the forum) before posting the question. It looks like I am missing or not understanding something. I am setting INTERMDISABLE signal high (in addition to specifying DIFF_TERM FALSE), but the input still adds termination resistance to the bus.

 

I am pretty sure it is the input, because when I reset the FPGA by reloading the configuration, the termination disappears for the time the FPGA is reloaded.

 

Regards,

Vlad

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Participant vapostolov
Participant
5,848 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

I tried using IOBUFDS and I still can't disable the termination.

Anyone having suggestion what could be wrong?

I am starting to think it could be a bug in Vivado.

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Participant vapostolov
Participant
5,794 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

I downloaded the latest and greatest Vivado 2015.2.1 and I still have termination enabled even though I’ve got

get_property DIFF_TERM [get_ports PAD_COMMS_P]
0
get_property DIFF_TERM [get_ports PAD_COMMS_N]
0

from the implemented design.

 

I changed the design to permanently drive the tri-state enable buffer pin high (commsTristateEn <= ‘1’), which permanently tri-sates the buffer:

PAD_COMMS_BUF : IOBUFDS
generic map (
    DIFF_TERM => FALSE, -- Differential termination (TRUE/FALSE)
    IBUF_LOW_PWR => TRUE, -- Low Power - TRUE, HIGH Performance = FALSE
    IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
    SLEW => "SLOW") -- Specify the output slew rate
port map (
    O => commsUartRx, -- Buffer output
    IO => PAD_COMMS_P, -- Diff_p inout (connect directly to top-level port)
    IOB => PAD_COMMS_N, -- Diff_n inout (connect directly to top-level port)
    I => commsUartTx, -- Buffer input
    T => commsTristateEn -- 3-state enable input, high=input, low=output
);

With this design, I measured 94.9 ohms between the two pins of the differential pair with a multimeter, which confirms the termination is enabled.

The differential pair is defined like this in my xdc file:

set_property IOSTANDARD LVDS_25 [get_ports PAD_COMMS_P]
set_property IOSTANDARD LVDS_25 [get_ports PAD_COMMS_N]
set_property DIFF_TERM FALSE [get_ports PAD_COMMS_P]
set_property DIFF_TERM FALSE [get_ports PAD_COMMS_N]
set_property PACKAGE_PIN F14 [get_ports PAD_COMMS_N]

Here is a photo showing the part number I am using:

artix.jpg

 

Could someone from Xilinx confirm that I am not the first one trying to use BLVDS buffer with disabled internal input termination.

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Participant vapostolov
Participant
5,792 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

By the way the Artix chips were purchased from Digi-Key, so they should be genuine Xilinx parts.

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Participant vapostolov
Participant
5,731 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

Could someone from Xilinx confirm that I am not the first one trying to use BLVDS buffer with disabled internal input termination.

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Highlighted
Participant vapostolov
Participant
5,691 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

It sounds like no one from Xilinx is able to answer my question.

Is there anyone who is successfully using BLVDS input buffer with disabled internal termination?

 

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Participant vapostolov
Participant
5,657 Views
Registered: ‎08-06-2013

Re: Not able to disable input termination on BLVDS input

 

After three weeks of frustration with this issue, I finally have a resolution from a Xilinx engineer (thanks Digi-Key for pushing Xilinx to pay attention on this problem).
For other users with the same issue, this was a code error. The IOBUFDS declared the IOSTANDARD correctly to BLVDS in the VHDL code

PAD_COMMS_BUF : IOBUFDS
generic map (
    DIFF_TERM => "FALSE", -- Differential termination (TRUE/FALSE)
    IBUF_LOW_PWR => TRUE, -- Low Power - TRUE, HIGH Performance = FALSE
    IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
    SLEW => "SLOW") -- Specify the output slew rate
port map (
    O => commsUartRx, -- Buffer output
    IO => PAD_COMMS_P, -- Diff_p inout (connect directly to top-level port)
    IOB => PAD_COMMS_N, -- Diff_n inout (connect directly to top-level port)
    I => commsUartTx, -- Buffer input
    T => commsTristateEn -- 3-state enable input, high=input, low=output
);

but in in the xdc file (as seen in the earlier posts) I was declaring the same buffers as LVDS:

set_property IOSTANDARD LVDS_25 [get_ports PAD_COMMS_P]
set_property IOSTANDARD LVDS_25 [get_ports PAD_COMMS_N]


It appeared that Vivado ignored the conflict and considered the xdc file as a higher priority, hence the input termination was ON. Vivado also was ignorring

set_property DIFF_TERM FALSE [get_ports PAD_COMMS_P]
set_property DIFF_TERM FALSE [get_ports PAD_COMMS_N]


While this was a code error, it exposed a bug in Vivado. Vivado (2014.2 and the latest 2015.2) were incorrectly reporting that there was no termination on the input buffer:

get_property DIFF_TERM [get_ports PAD_COMMS_P]
0
get_property DIFF_TERM [get_ports PAD_COMMS_N]
0

Vivado 2014.2 showed 122 warnings, 619 infos and 297 status messages for the design but none of them indicated the conflicting IOSTANDARD declaration.
With the latest Vivado 2015.2 it was even worse. The number of warnings for the same design increased to 984, the infos to 7,351 and the status messages to 623 and still no indication of the conflicting IOSTANDARD declaration.

 

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Scholar pedro_uno
Scholar
5,623 Views
Registered: ‎02-12-2013

Re: Not able to disable input termination on BLVDS input

Hey Vap,

Did you ever get an answer to this? Did Xilinx admit a bug?
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DSP in hardware and software
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Scholar pedro_uno
Scholar
3,318 Views
Registered: ‎02-12-2013

Re: Not able to disable input termination on BLVDS input

I often want to get fine control of my FPGA I/O so I tried a micro experiement.  I found that Vivado synthesis does not accept the generic map syntax in your code example, DIFF_TERM => "FALSE".  It wants a boolean not a string now.

 

I compiled the below example in Vivado 2015.2 and looked at the device view of the compiled design.  I found that I could turn on and off the DIFF_TERM by changing the generic value between true and false.

 

I hope this helps.

 

    Pete

 

--------------------------------

library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;

entity top is
port (
    t       : in    std_logic;
    d_io_p  : inout std_logic;
    d_io_n  : inout std_logic;
    d_out   : out   std_logic);
end entity top;

architecture rtl of top is
begin

    ibufds_inst : IOBUFDS
    generic map (
        DIFF_TERM  => false,
        IOSTANDARD => "BLVDS_25")
    port map (
        O   => d_out,
        IO  => d_io_p,
        IOB => d_io_n,
        I   => '1',
        T   => t);
    
end architecture rtl;

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DSP in hardware and software
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