UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor mbence76
Visitor
200 Views
Registered: ‎01-18-2019

Power consumption of a rarely called task

Jump to solution

Hello, 

I am new here and this is my first post.

I am using Vivado 2018.2,  Artix7 and SystemVerilog.

Does the hardware that actually performs a task (a task in SystemVerilog sense) consume energy when it is not active? 

Can I use tasks to consume power only when needed? 

Can it be that the synthesizer automatically employs the CE "pins" on the FFs in the task?

Thank you.

Miklos

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
170 Views
Registered: ‎09-17-2018

Re: Power consumption of a rarely called task

Jump to solution

Understand the entire device has some (not small) static power,

The few blocks than can be power gated (unused BRAM) are automatically powered down if not used.

Generally speaking FPGA devices do not have many static power saving features (too area intensive, so not done).  Instead clock gating is used to save dynamic power when a design is equipped to do so (the design uses clock gating provided by the BUFGCE).

Clock enables on the various tiles (DFF, BRAM, DSP, etc.) generally saves little dynamic power.

FPGA devices ar erarely used in low power applications, as they are not low power devices at all  (as compared to devices that are actually designed for low power applications).

l.e.o.

3 Replies
Moderator
Moderator
178 Views
Registered: ‎09-18-2014

Re: Power consumption of a rarely called task

Jump to solution

Hello New Here,

 

Yes, Vivado implementation tools should automatically performs clock gating on portions of your design where it best makes sense to do. Feel free to read the two white papers linked below for more information regarding this Xilinx tools feature.

 

https://www.xilinx.com/support/documentation/white_papers/wp389_Lowering_Power_at_28nm.pdf

 

https://www.xilinx.com/support/documentation/white_papers/wp370_Intelligent_Clock_Gating.pdf

 

 

Regards,

T

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Highlighted
Explorer
Explorer
171 Views
Registered: ‎09-17-2018

Re: Power consumption of a rarely called task

Jump to solution

Understand the entire device has some (not small) static power,

The few blocks than can be power gated (unused BRAM) are automatically powered down if not used.

Generally speaking FPGA devices do not have many static power saving features (too area intensive, so not done).  Instead clock gating is used to save dynamic power when a design is equipped to do so (the design uses clock gating provided by the BUFGCE).

Clock enables on the various tiles (DFF, BRAM, DSP, etc.) generally saves little dynamic power.

FPGA devices ar erarely used in low power applications, as they are not low power devices at all  (as compared to devices that are actually designed for low power applications).

l.e.o.

Visitor mbence76
Visitor
149 Views
Registered: ‎01-18-2019

Re: Power consumption of a rarely called task

Jump to solution
Thank you indeed for your swift response.
0 Kudos