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Selecting package pin for reset

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Visitor
Posts: 29
Registered: ‎11-23-2017
Accepted Solution

Selecting package pin for reset

I am using an XC7A100T, on a board with no board file.

The block automation in Vivado creates a port called reset_rtl_0 that is hooked up to the clocking wizard.

However I still need to define the i/o port pin and i/o standard for this port.

Please assist.


Accepted Solutions
Scholar
Posts: 434
Registered: ‎08-07-2014

Re: Selecting package pin for reset

[ Edited ]

You are talking about a system reset input I guess.For my AC701 board I had used the following.

 

#AC701 CPU Reset
set_property PACKAGE_PIN U4             [get_ports glbl_rst_i]  # active low reset input
set_property IOSTANDARD  LVCMOS15 [get_ports glbl_rst_i]

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FPGA enthusiast!
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All Replies
Scholar
Posts: 434
Registered: ‎08-07-2014

Re: Selecting package pin for reset

[ Edited ]

You are talking about a system reset input I guess.For my AC701 board I had used the following.

 

#AC701 CPU Reset
set_property PACKAGE_PIN U4             [get_ports glbl_rst_i]  # active low reset input
set_property IOSTANDARD  LVCMOS15 [get_ports glbl_rst_i]

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FPGA enthusiast!
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Moderator
Posts: 108
Registered: ‎05-02-2017

Re: Selecting package pin for reset

 

hi @simchask,

 

I believe that reset_rtl_0 is reset sequence , in -order to use the reset  in your design. you need to define that in ports along with IO standard in XDC file for reset usage.

 

 

ta

sekhar 

Visitor
Posts: 29
Registered: ‎11-23-2017

Re: Selecting package pin for reset

Thanks!

I didn't understand that this reset should be hooked up to the reset push button switch. I thought it was some electrical signal the FPGA should be accepting from the clock. Is there a document that specifies the appropriate IO standards?

Scholar
Posts: 434
Registered: ‎08-07-2014

Re: Selecting package pin for reset

Is there a document that specifies the appropriate IO standards?

 

Part number-wise I am not sure (e.g. XC7A100T).

But board number-wise yes, for e.g. AC701 (you have to see the User Guide for this board UG952).

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FPGA enthusiast!
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