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Explorer
Explorer
9,056 Views
Registered: ‎08-07-2013

Should I care about some unexpected Gated Clock warnings in DRC report?

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Dear Sir,

 

I've gotten some warnings as below in the DRC report.  It shows me that Some usual nets

are used as a clock nets.  Should I care about the issue?  It seems no difference

from other in verilog code.  Why some of them are implemented as a clock net?

Gated Clock is easy to cause some timing issues, isn't it?  Especially, it is an 

unexpected clock net.  The function may not be as what we expected.

How should I handle those warnings while getting them in .drc report?

Thanks.

 

WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/sdi_framer/vcnt[12]_Y_1[12]_OR_21668_o is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/reg_file/sys_rstn_i_SoftRst_AND_295_o is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/eth_atpg/byte_cnt[10]_GND_24_o_equal_27_o is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/rx_mimic_host/current_reg_2_G is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/ram_block/jpg_mem_ctrl/n0694<4> is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/rx_mimic_host/current_add_12_G is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/ram_block/jpg_mem_ctrl/data_in_rdy_1_data_in_rdy_MUX_6776_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
rx_top_eth/rx_mimic_host/_n0816 is sourced by a combinatorial pin. This is
not good design practice. Use the CE pin to control the loading of data into
the flip-flop.

 

 

 

Peter Chang

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1 Solution

Accepted Solutions
Historian
Historian
17,285 Views
Registered: ‎01-23-2009

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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The G input of a latch is a "clock". So a latch with a combinatorial signal connected to its G input will give this warning. Any code like

 

always @(*)

begin

  if (a || b)

      c <= d;

end

 

will generate a gated clock input warning.

 

Avrum

8 Replies
Moderator
Moderator
9,037 Views
Registered: ‎07-01-2015

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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Hi @peterchang0708,

 

Please go through following links:

http://www.xilinx.com/support/answers/46375.html

http://www.xilinx.com/support/answers/33554.html

 

Hope this addresses your concern.

 

Thanks,
Arpan

Thanks,
Arpan
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Explorer
Explorer
9,018 Views
Registered: ‎08-07-2013

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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Hi Arpan,

 

Thanks for your infomation.  It is useful, but for my case, at least.  The verilog code may not be so straight forward

as that shown in the document for the gated clock.  I don't know why the code will have some gated clock.

Is it possible that the gated clock may for a latch in design?

 

 

Peter Chang

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Moderator
Moderator
9,014 Views
Registered: ‎07-01-2015

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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Hi @peterchang0708,

 

Are you using latch for clock gating?

 

Thanks,
Arpan

Thanks,
Arpan
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Historian
Historian
17,286 Views
Registered: ‎01-23-2009

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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The G input of a latch is a "clock". So a latch with a combinatorial signal connected to its G input will give this warning. Any code like

 

always @(*)

begin

  if (a || b)

      c <= d;

end

 

will generate a gated clock input warning.

 

Avrum

Explorer
Explorer
8,913 Views
Registered: ‎08-07-2013

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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Hi Avrum,

 

Thanks for your information.  I think so.  Normally, we don't implement a case for a Flip-Flop as that in the document,

but a combinational circuit as you said.  It may be compiled into a latch with gated clock.  Should I use an alternative

expression in my code as below?

 

always @(*)

c = (a||b)? d : c;

 

or,

assign c = (a || b)? d : c;

 

Thanks.

 

Peter Chang

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Highlighted
Historian
Historian
8,893 Views
Registered: ‎01-23-2009

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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All of these pieces of code are essentially identical.

 

You are explicitly coding "when a||b is false, c should keep its old value". How exactly can c keep its old value? This is exactly what a latch is!

 

So it doesn't matter whether how you code them - all three of the examples (my original and your two new ones) are latches (and if they are not, then the tools will complain about them since they contain combinatorial feedback).

 

In RTL coding, all coding must end up inferring flip-flops or combinatorial logic (without feedback) - you must think hardware!

 

Avrum

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Explorer
Explorer
8,841 Views
Registered: ‎08-07-2013

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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Hi Arpan,

 

I am using some code in a style as below.

 

always @(*)

begin

  if (a || b)

      c <= d;

end

 

I guess those all compiled into a latch.

Then, it may have gated clock.

 

 

Peter 

 

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Explorer
Explorer
8,840 Views
Registered: ‎08-07-2013

Re: Should I care about some unexpected Gated Clock warnings in DRC report?

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Hi Avrun,

 

Agree.  Thanks for your answer.

 

 

Peter Chang

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