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630 Views
Registered: ‎08-14-2018

Spartan 7: can't adjust full range of IDELAYE2 for ISERDESE2

Hello!

I have a problem with controlling delay value in LVDS receiver which was created in SelectIO Wizard.

My project using in_delay_data_ce and in_delay_data_inc to change delay setting, and in_delay_tap_out used to control actual value. First of all, I can't understand how to control this value precisely. The only way I found is activation of in_delay_data_ce pin and when in_delay_tap_out value become as wanted then in_delay_data_ce goes 0. Is it correct to put _ce into zero state?

 

Most interesting trouble is that I can't set value higher than 8 or lower than 24. Only 0..8 and 24..31 values accessible at in_delay_tap_out. Why? My LVDS speed is 400 mpbs.

 

However, I see the following parameters:

     IDELAYE2
       # (
         .CINVCTRL_SEL           ("FALSE"),                            // TRUE, FALSE
         .DELAY_SRC              ("IDATAIN"),                          // IDATAIN, DATAIN
         .HIGH_PERFORMANCE_MODE  ("FALSE"),                            // TRUE, FALSE
         .IDELAY_TYPE            ("VAR_LOAD"),              // FIXED, VARIABLE, or VAR_LOADABLE
         .IDELAY_VALUE           (15),                  // 0 to 31
         .REFCLK_FREQUENCY       (200.0),
         .PIPE_SEL               ("FALSE"),
         .SIGNAL_PATTERN         ("DATA"))

But I use outer PLL which makes 400 and 50 MHz from 200 MHz. I suppose these settings incorrect and I there should be 400 in refclk_frequency. I suspect source of such problem here.

 

 

Also I found another topic https://forums.xilinx.com/t5/7-Series-FPGAs/Phase-recovery-with-ISERDESE2/m-p/868231/highlight/true#M27617

average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps

How these values calculated?

 

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4 Replies
589 Views
Registered: ‎01-08-2012

Re: Spartan 7: can't adjust full range of IDELAYE2 for ISERDESE2

Also I found another topic https://forums.xilinx.com/t5/7-Series-FPGAs/Phase-recovery-with-ISERDESE2/m-p/868231/highlight/true#M27617

average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps

How these values calculated?

 

I notice that the product of the reference clock frequency and the average tap delay (e.g. 400MHz * 39ps) is a dimensionless constant, 1/64.  This leads me to guess that there are 64 taps with the total delay of those 64 taps being servoed to one period of the reference clock.

The internal details are probably somewhat different (and not available without an NDA!), but I think that's roughly what the numbers mean.

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538 Views
Registered: ‎08-14-2018

Re: Spartan 7: can't adjust full range of IDELAYE2 for ISERDESE2


@allanherriman wrote:

Also I found another topic https://forums.xilinx.com/t5/7-Series-FPGAs/Phase-recovery-with-ISERDESE2/m-p/868231/highlight/true#M27617

average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps

How these values calculated?

 

I notice that the product of the reference clock frequency and the average tap delay (e.g. 400MHz * 39ps) is a dimensionless constant, 1/64.  This leads me to guess that there are 64 taps with the total delay of those 64 taps being servoed to one period of the reference clock.

The internal details are probably somewhat different (and not available without an NDA!), but I think that's roughly what the numbers mean.


IDELAYE2 in Spartan 7 provide only 32 taps. SelectIO Wizard pass slow clock .C(clk_div_in) to C clock input, it's 50 MHz in my case (50x8 = 400). Which reference clock value in my case? 400? But delay block accepts only slow clock 50 MHz and I clearly see that fact (clk_div_in connected to C input of IDELAYE2). When I set REFCLK_FREQUENCY to 50.0 it says this value is not correct, acceptable values around 100 200 and 400 MHz. Strange. I completely don not understand how this delay block functioning. Is there are more detailed information about its architecture?

 

Actually, I don't care about exact delay values, my idea is to find left and right margins where calibration sequence will fail and then set up medium value of delay. The problem is that I can't set values more than 8 or less than 24, only half of full range accessible. It able to increment from 0 to 8 but then it stuck at 8.

 

I suppose 39 ps delay is for 64 taps and 78 ps for 32 taps - am I right???

Symbol time at 400 mbps is 2.5 ns. Half range 16/32 accessible to me. 16 * 78 ps = 1248 ps, exactly half of symbol time.

 

May this be a reason that delay value limited to 16 steps of 32? Some undocumented hidden limiting mechanism? In fact, ability to shift +-0.25 of symbol time ought to be enough to set sampling time at center of data symbol.

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545 Views
Registered: ‎08-14-2018

Re: Spartan 7: can't adjust full range of IDELAYE2 for ISERDESE2


@allanherriman wrote:

Also I found another topic https://forums.xilinx.com/t5/7-Series-FPGAs/Phase-recovery-with-ISERDESE2/m-p/868231/highlight/true#M27617

average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps

How these values calculated?

 

I notice that the product of the reference clock frequency and the average tap delay (e.g. 400MHz * 39ps) is a dimensionless constant, 1/64.  This leads me to guess that there are 64 taps with the total delay of those 64 taps being servoed to one period of the reference clock.

The internal details are probably somewhat different (and not available without an NDA!), but I think that's roughly what the numbers mean.


IDELAYE2 in Spartan 7 provide only 32 taps. SelectIO Wizard pass slow clock .C(clk_div_in) to C clock input, it's 50 MHz in my case (50x8 = 400). Which reference clock value in my case? 400? But delay block accepts only slow clock 50 MHz and I clearly see that fact (clk_div_in connected to C input of IDELAYE2). When I set REFCLK_FREQUENCY to 50.0 it says this value is not correct, acceptable values around 100 200 and 400 MHz. Strange. I completely don not understand how this delay block functioning. Is there are more detailed information about its architecture?

 

Actually, I don't care about exact delay values, my idea is to find left and right margins where calibration sequence will fail and then set up medium value of delay. The problem is that I can't set values more than 8 or less than 24, only half of full range accessible. It able to increment from 0 to 8 but then it stuck at 8.

 

I suppose 39 ps delay is for 64 taps and 78 ps for 32 taps - am I right?

Symbol time at 400 mbps is 2.5 ns. Half range 16/32 accessible to me. 16 * 78 ps = 1248 ps, exactly half of symbol time.

 

May this be a reason that delay value limited to 16 steps of 32? Some undocumented hidden limiting mechanism? In fact, ability to shift +-0.25 of symbol time ought to be enough to set sampling time at center of data symbol.

0 Kudos
565 Views
Registered: ‎08-14-2018

Re: Spartan 7: can't adjust full range of IDELAYE2 for ISERDESE2


@allanherriman wrote:

IDELAYE2 in Spartan 7 provide only 32 taps. SelectIO Wizard pass slow clock .C(clk_div_in) to C clock input, it's 50 MHz in my case (50x8 = 400). Which reference clock value in my case? 400? But delay block accepts only slow clock 50 MHz and I clearly see that fact (clk_div_in connected to C input of IDELAYE2). When I set REFCLK_FREQUENCY to 50.0 it says this value is not correct, acceptable values around 100 200 and 400 MHz. Strange. I completely don not understand how this delay block functioning. Is there are more detailed information about its architecture?

 

Actually, I don't care about exact delay values, my idea is to find left and right margins where calibration sequence will fail and then set up medium value of delay. The problem is that I can't set values more than 8 or less than 24, only half of full range accessible. It able to increment from 0 to 8 but then it stuck at 8.

 

I suppose 39 ps delay is for 64 taps and 78 ps for 32 taps - am I right?

Symbol time at 400 mbps is 2.5 ns. Half range 16/32 accessible to me. 16 * 78 ps = 1248 ps, exactly half of symbol time.

 

May this be a reason that delay value limited to 16 steps of 32? Some undocumented hidden limiting mechanism? In fact, ability to shift +-0.25 of symbol time ought to be enough to set sampling time at center of data symbol.

0 Kudos