09-21-2017 06:36 AM
I am using a FMC204 with DAC5682z in my project. I have interfaced it with Virtex-7 FPGA board. I am generating a clock from the FMC chip and feeding it to MMCM to generate the CLK (250 MHz DDR) and CLKDIV (125MHz) for OSERDES. I use OSERDES to generate Data, Sync and DCLK. I am trying to generate a 1MHz square wave on FPGA based on CLKDIV using counters. Output pattern is xAAAA and x5555.
I configure the AD9517 chip on FMC through a microblaze SPI(using system clock) which would generate the CLKIN(500MHz) to DAC and also sends ref. Clk to FPGA. Then I do the following steps for DAC configuration:
After following this procedure, I could see the FIFO_ERR bit is always set and I am not able to come out of the error. I have tried with various modes of Dual DAC and single DAC. Only in Single DAC mode with FIR disabled and SW sync, the Status4 returns 0. But the waveform would still be not the expected square wave.
I would be really glad if you could provide some help regarding this.
I would be really grateful If someone has worked on 4DSP DAC FMCs could help me with the possible pitfalls.
Thanks in advance,
09-22-2017 03:01 AM
I have simulated the data generation part and sending it out of OSERDES output. The data going into DAC FIFO is as expected and should be producing a square wave.