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Visitor lynume
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1,110 Views
Registered: ‎05-30-2018

Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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I'm trying to use the SelectIO interface wizard and I have the reset coming up after the reset for the clocks giving it plenty of time but I don't see anything coming out of the serdes  output even though in simulation I see the data out of the lvds_25 p and n signals.

 

 

 

 

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Adventurer
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1,174 Views
Registered: ‎05-23-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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Have a look at xapp585: https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

 

Using OSerdes in DDR-Mode with BUFIO/BUFR, you're usually able to approach 1200Mbps. It might be a little bit less depending on PCB-Quality (Clocks, Power-Supply, Routing of differential signals).

 

Zynq7010 is equivalent to the Artix 7 Series in regards to FPGA logic. Have a look at the speedgrade of your device as well.

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Moderator
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Registered: ‎04-18-2011

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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Hi @lynume

 

If it seems to behave normally in your simulation then the chances are that the logic is good. 

Can you route the input to an output and make sure that electrically the input present at the output of IBUFDS?

can you share the settings you used in the wizard? what is the data rate?

 

Keith 

 

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Visitor lynume
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Registered: ‎05-30-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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I figured out what the issue was, it was that the bank needs to be set to 2.5V for LVDS2_5 to transmit.  But I have another problem, will I have issues if my clock is 100 mhz, what's the max speed of the LVDS signals from the XC7z010 fpga

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Adventurer
Adventurer
1,175 Views
Registered: ‎05-23-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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Have a look at xapp585: https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

 

Using OSerdes in DDR-Mode with BUFIO/BUFR, you're usually able to approach 1200Mbps. It might be a little bit less depending on PCB-Quality (Clocks, Power-Supply, Routing of differential signals).

 

Zynq7010 is equivalent to the Artix 7 Series in regards to FPGA logic. Have a look at the speedgrade of your device as well.

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Visitor lynume
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959 Views
Registered: ‎05-30-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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Thanks, I'll see about using in DDR

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Visitor lynume
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Registered: ‎05-30-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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Hi so I'm seeing that using the select io wizard and the using the oserdes with a XZ7z010 FPGA that I'm not really getting a true lvds signal, my signal changes everytime I change one of the input bits to the serializer and seems to be dependent on the frequency of the input signal I send into the signal which seems to affect the output of the serializer.

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Visitor lynume
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Registered: ‎05-30-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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I'm using DDR how can I get a true lvds signal, I'm getting this what is attached

FPGA_Screen_Capture.bmp
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Visitor lynume
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Registered: ‎05-30-2018

Re: Xilinx SERDES SelectIO interface LVDS Zync series 7 FPGA

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The clk speed going into the oserdes is 50 Mhz, the data on each input pin the highest is 1 Mhz, so data rate is probably around 50Mbps.  I've atttached the serdes settings.

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