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Visitor omer.kvitel
Visitor
194 Views
Registered: ‎05-07-2018

ZYNQ7000: LVDS IF on high-performance (HP) and high-range (HR) I/O banks

Hi

I have a question on the following issue:

I would like to know if I can implement LVDS IF on a ZYNQ7000 (HP/HR IO banks) and connect to the selectIO an internal clock coming from the PL or PS?

Meaning drive the reference clock to the selectIO from internal PLL.

From the selectIO user guide, page 154:

The only valid clocking arrangements for the ISERDESE2 block using the networking interface type are:

• CLK driven by BUFIO, CLKDIV driven by BUFR

• CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL

When using a MMCM to drive the CLK and CLKDIV of the ISERDESE2, the buffer types suppling the ISERDESE2 can not be mixed.

For example, if CLK is driven by a BUFG, then CLKDIV must be driven by a BUFG as well.

Alternatively, the MMCM can drive the ISERDESE2 though a BUFIO and BUFR.

 

As it seems, it is possible - I will appreciate if someone can give his opinion as well.

 

Regards

Omer

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3 Replies
Moderator
Moderator
91 Views
Registered: ‎04-18-2011

Re: ZYNQ7000: LVDS IF on high-performance (HP) and high-range (HR) I/O banks

Normally the data you are trying to capture has a synchronous relationship to some clock in the system. 

How can a clock from the PS be synchronous to this interface 

Where is this internal PL clock coming from??

 

 

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Visitor omer.kvitel
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Registered: ‎05-07-2018

Re: ZYNQ7000: LVDS IF on high-performance (HP) and high-range (HR) I/O banks

Hi

The reference clock for each FPGA will come on board.

The internal PLL will match the frequencies of LVDS IF in each FPGA to be identical.

Meaning :

1. The external reference clock to the PL do not match but internal PLL match the frequency.

2. The external reference clock to the PLL is identical, the internal PLL match the frequencies.

 

Regards

Omer

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Moderator
Moderator
37 Views
Registered: ‎04-18-2011

Re: ZYNQ7000: LVDS IF on high-performance (HP) and high-range (HR) I/O banks

Two systems can run at the same frequency and not be considered synchronous. 

It is not clear from your reply... 

A diagram of the interface and your proposed clocking would be useful.

It seems like you are going to provide a common reference clock to two FPGAs.

Use this reference clock to feed a PLL or indeed an MMCMs in each device to create the capture clock and parallel clock for the interfaces. 

Then you expect to have the ability to have data in one sent to the other over an LVDS link and capture it just with your MMCM output clocks in the other.

 The answer to is in Theory yes, but in practice you can't be sure that the phase of the two clock managers is aligned. 

 

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