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Observer eldercosta
Observer
154 Views
Registered: ‎10-31-2017

Zynq PL: inferring LVDS as a bus

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Hello.

 

I have a design with 34 LVDS inputs and I would like to treat them as a bus, i.e. connecting them internally through a generate clause (VHDL) and have the synthesizer to resolve it to LVDS pairs with the pin constraints configuration file.

 

I mean, say the single-ended inputs in my design are something like

MY_LVDS_BUS : out std_logic_vector (33 downto 0);

 

and I want to connect it to an MY_LVDS_BUS input bus on the Zynq bd. Then I would like to have it mapped to MY_LVDS_BUS[i]_P and MY_LVDS_BUS[i]_N in the device.

 

Is it possible?

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1 Solution

Accepted Solutions
94 Views
Registered: ‎01-22-2015

Re: Zynq PL: inferring LVDS as a bus

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@eldercosta

I'm not sure that I understand the question.   Maybe the following is what you want?

Use the VHDL signal vector in your design: 

signal MY_LVDS_BUS : std_logic_vector (33 downto 0); 

Add the following outputs to the top-level VHDL module in your design: 

MY_LVDS_BUS_P : out std_logic_vector (33 downto 0);
MY_LVDS_BUS_N : out std_logic_vector (33 downto 0); 

Use the differential signal output buffer, OBUFDS, by instantiating it into your VHDL design as follows (see UG953 for details): 

GEN1: for i in 0 to 33 generate 
   MY_LVDS: OBUFDS
      generic map(
         IOSTANDARD => "LVDS", 
         SLEW => "SLOW") 
      port map(
         O => MY_LVDS_BUS_P(i),
         OB => MY_LVDS_BUS_N(i),   
         I => MY_LVDS_BUS(i) 
   );     
end generate GEN1; 

Write constraints that look something like the following: 

set_property IOSTANDARD LVDS [get_ports {MY_LVDS_BUS_P[*]}]
set_property IOSTANDARD LVDS [get_ports {MY_LVDS_BUS_N[*]}]
set_property PACKAGE_PIN U12 [get_ports {MY_LVDS_BUS_P[33]}]
set_property PACKAGE_PIN AB13 [get_ports {MY_LVDS_BUS_P[32]}]
# Here, specify P-side pin for all other LVDS pin-pairs (31 down to 0).
# You do not need to specify N-side pins

Cheers,
Mark

 

2 Replies
95 Views
Registered: ‎01-22-2015

Re: Zynq PL: inferring LVDS as a bus

Jump to solution

@eldercosta

I'm not sure that I understand the question.   Maybe the following is what you want?

Use the VHDL signal vector in your design: 

signal MY_LVDS_BUS : std_logic_vector (33 downto 0); 

Add the following outputs to the top-level VHDL module in your design: 

MY_LVDS_BUS_P : out std_logic_vector (33 downto 0);
MY_LVDS_BUS_N : out std_logic_vector (33 downto 0); 

Use the differential signal output buffer, OBUFDS, by instantiating it into your VHDL design as follows (see UG953 for details): 

GEN1: for i in 0 to 33 generate 
   MY_LVDS: OBUFDS
      generic map(
         IOSTANDARD => "LVDS", 
         SLEW => "SLOW") 
      port map(
         O => MY_LVDS_BUS_P(i),
         OB => MY_LVDS_BUS_N(i),   
         I => MY_LVDS_BUS(i) 
   );     
end generate GEN1; 

Write constraints that look something like the following: 

set_property IOSTANDARD LVDS [get_ports {MY_LVDS_BUS_P[*]}]
set_property IOSTANDARD LVDS [get_ports {MY_LVDS_BUS_N[*]}]
set_property PACKAGE_PIN U12 [get_ports {MY_LVDS_BUS_P[33]}]
set_property PACKAGE_PIN AB13 [get_ports {MY_LVDS_BUS_P[32]}]
# Here, specify P-side pin for all other LVDS pin-pairs (31 down to 0).
# You do not need to specify N-side pins

Cheers,
Mark

 

Observer eldercosta
Observer
65 Views
Registered: ‎10-31-2017

Re: Zynq PL: inferring LVDS as a bus

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Hello, Mark.

 

It's been a while, with another tool and (non Xilinx) FPGA  but I am quite sure I could declare an LVDS in or out without the _[P|N] suffix and the pin constraint was all that the tool needed to define a differential pair (not saying Vivado's or Xilinx's way is worse, just different).

 

Anyway your answer provides a way nearly as simple to achieve what I need.

 

Thank you very much.

 

Elder.

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