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Contributor
Contributor
607 Views
Registered: ‎07-18-2014

question about lvds clock termination

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Hi,

On the KC705,VC707 and VC709 EVM,the System Clock (SYSCLK_P and SYSCLK_N) is generated by SiT9102(LVDS 200 MHz Oscillator),but the way of termination is different.

 

On KC705 and VC707,the LVDS clock is DC coupled with a LVDS termination resistor

VC707.jpg

but the VC709, the LVDS clock is AC coupled without termination resistor

VC709.jpg

What is the difference between the two termination ways?

 

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Community Manager
Community Manager
547 Views
Registered: ‎07-23-2015

Re: question about lvds clock termination

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@chenxuol This AR :https://www.xilinx.com/support/answers/43989.html captures the above points described. You may want to refer it to get a better understanding. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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Explorer
Explorer
585 Views
Registered: ‎10-05-2010

Re: question about lvds clock termination

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The top circuit is the normal LVDS termination, and is used when the voltage of the LVDS source matches the bank voltage; for example, a 2.5V LVDS oscillator driving a bank with Vcco = 2.5V.

 

That same 2.5V LVDS oscillator can also drive a bank with a Vcco other than 2.5V if the LVDS driver meets certain criteria (from UG471):

• The optional internal differential termination is not used (DIFF_TERM = FALSE,
  which is the default value).
• The differential signals at the input pins meet the VIN requirements in the
  Recommended Operating Conditions table of the specific device family data sheet.
• The differential signals at the input pins meet the VIDIFF (min) requirements in the
  corresponding LVDS or LVDS_25 DC specifications tables of the specific device family
  data sheet.
• For HR I/O banks in bidirectional configuration, internal differential termination is
  always used.

The VC709 termination ensures that the LVDs driver meets the Vin and Vidiff requirements.

See the description of LVDS and LVDS_25 in UG471, chapter 1.

 

---

Joe Samson

 

 

 

Tags (2)
Scholar drjohnsmith
Scholar
577 Views
Registered: ‎07-09-2009

Re: question about lvds clock termination

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Generally,

 

if its a clock, then AC couple,

 

It takes away all the concerns that can occur, start up , power sequencing, dc offsets , power noise 

 

IMHO, the designs that tend to not be ac coupled are either not a clock, or are a mistake....

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Community Manager
Community Manager
548 Views
Registered: ‎07-23-2015

Re: question about lvds clock termination

Jump to solution

@chenxuol This AR :https://www.xilinx.com/support/answers/43989.html captures the above points described. You may want to refer it to get a better understanding. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
0 Kudos