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Visitor taller
Visitor
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Registered: ‎08-06-2018

xapp523 Mmcm phase shift problem

Hi, all!
I am trying to implement the xapp523 on 7 series. None of the MMCMs are showing a clock for any of the signals that have USE_FINE_PS     => TRUE. All other MMCM clock outputs (with USE_FINE_PS set to FALSE) generate clocks.

Why is this and how do I fix it?

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Moderator
Moderator
505 Views
Registered: ‎04-18-2011

Re: xapp523 Mmcm phase shift problem

Is this in hardware or simulation? Is the psclk running?
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Visitor
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Registered: ‎08-06-2018

Re: xapp523 Mmcm phase shift problem

1. In simulator. I'm using Vivado 2018.1, target device - xc7s50.
2. PSCLK is not running, but...
In "Receiver.vhd" PSCLK connected to IntClkDiv, that in "RxGenClockMod.vhd" through BUFG connected to CLKOUT3.
When CLKOUT3_USE_FINE_PS = TRUE and CLKOUT4_USE_FINE_PS = TRUE, there is no generating signal on both outputs CLKOUT3 and CLKOUT4. PSCLK none.
When CLKOUT3_USE_FINE_PS = TRUE and CLKOUT4_USE_FINE_PS = FALSE, there is no generating signal on output CLKOUT3, CLKOUT4 is running. PSCLK none.
When CLKOUT3_USE_FINE_PS = FALSE and CLKOUT4_USE_FINE_PS = TRUE, clocks are generating on both outputs CLKOUT3 and CLKOUT4, but in this case phase shifting applied on CLKOUT4 only.


P.S. English is not my native language, so please be kind to my mistakes.
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