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Newbie
Newbie
1,467 Views
Registered: ‎04-19-2018

AWREADY not going high in AXI Quad SPI v3.2

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Hi All,

 

Here is a question regarding AXI Quad SPI v3.2 IP in Vivado 2017.4

 

I am driving the ip with a state machine.

In simulation, I see that a read returns the reset value of the register addr 0x60 value = 0x180 as expected, but an attempted write does not work because the AWREADY stays low.  I have attached a screenshot of a simulation waveform showing the successful read and the stalled write.  I am also attaching a screenshot of the vivado configuration of the IP.  I am quite sure I have wired the fsm together correctly, but just in case, I have copied and pasted the instantiations of the two modules in a code snippet below.

 

Any help would be appreciated!

 

logic ext_spi_clk;
logic s_axi_aclk;
logic s_axi_aresetn;
logic [6:0]s_axi_awaddr;
logic s_axi_awvalid;
logic s_axi_awready;
logic [31:0]s_axi_wdata;
logic [3:0]s_axi_wstrb;
logic s_axi_wvalid;
logic s_axi_wready;
logic [1:0]s_axi_bresp;
logic s_axi_bvalid;
logic s_axi_bready;
logic [6:0]s_axi_araddr;
logic s_axi_arvalid;
logic s_axi_arready;
logic [31:0]s_axi_rdata;
logic [1:0]s_axi_rresp;
logic s_axi_rvalid;
logic s_axi_rready;
logic io0_i;
logic io0_o;
logic io0_t;
logic io1_i;
logic io1_o;
logic io1_t;
logic sck_i;
logic sck_o;
logic sck_t;
logic [0:0]ss_i;
logic [0:0]ss_o;
logic ss_t;
logic ip2intc_irpt;

assign ext_spi_clk = sys_clk;
assign s_axi_aclk = sys_clk;
assign s_axi_aresetn = ~sys_rst;

 

//for now tie the inputs of the tri states to zero

assign io0_i = '0;
assign io1_i = '0;
assign ss_i[0] = '0;


axi_control axi_control(.*);

axi_spi spi_master(.*);

 

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waveform.png
aqspi_config.png
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Xilinx Employee
Xilinx Employee
1,582 Views
Registered: ‎08-02-2011
Hello,

What's happening on wvalid/wready? Can you run a test by asserting wvalid at the same time as awvalid?
www.xilinx.com

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Xilinx Employee
Xilinx Employee
1,583 Views
Registered: ‎08-02-2011
Hello,

What's happening on wvalid/wready? Can you run a test by asserting wvalid at the same time as awvalid?
www.xilinx.com

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Visitor
Visitor
1,426 Views
Registered: ‎04-24-2018

Thank you!

 

That indeed solved the issue.

 

Is this always the necessary protocol for AXI Lite?

 

I was using an AXI burst write example from the ARM protocol spec (diagram attached) ... shows awvalid going high before wvalid.

 

 

axi_write.png
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Xilinx Employee
Xilinx Employee
1,420 Views
Registered: ‎08-02-2011

I agree with you; I don't think this should be required according to spec. But I've seen it before with other cores :).

 

From my recollection of studying the matter, I believe it may be an ambiguity in the spec. One note on the subject is:

 

 

The dependency rules must be observed to prevent a deadlock condition. For example, a master must not
wait for AWREADY to be asserted before driving WVALID. A deadlock condition can occur if the slave is
waiting for WVALID before asserting AWREADY.

 

However, I could see the argument for interpreting the situation as: The master is not waiting for awready; it simply doesn't have data ready yet so can't assert wvalid. Then again... if it happens indefinitely, it's probably waiting on awready and thus a violation.

 

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Visitor
Visitor
1,245 Views
Registered: ‎07-03-2018

hi, mattyak89

do you solve it ?  i have the same question about axi-lite memroy

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Visitor
Visitor
1,234 Views
Registered: ‎07-03-2018

 

Set the awvalid and wvalid at the same time , but awready/wready keep 0  , so strange , where is the problem?

 

awready and wready.png

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