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Visitor
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Registered: ‎08-17-2016

AXI_QUAD_SPI in Kintex 7

Hi,

I have a working design in Kintex-7 410T. This design includes number of SERDES and a DDR3 interface. The Vivado flow goes smoothly. The bit stream is generated and working in my lab test.

Now, I want to add the AXI_QUAD_SPI IP (quad mode) in order to read and write the attached configuration Micron SPI flash. I follow the AXI_QUAD_SPI design example:

1. Instantiate the AXI_QUAD_SPI with STARTUPE2 enable.

2. Connect the io0_i/o/t, io1_i/o/t, io2_i/o/t, io3_i/o/t and ss_i/o/t to the IOBUF

3. Adding pin locations and buffer type (LVCMOS25) to my top level xdc constraint file.

Synthesis completed. But I got error during Implementation phase. The error message is as follow:

=========================================================

Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device

INFO: [Timing 38-35] Done setting XDC timing constraints.

ERROR: [Place 30-374] IO placer failed to find a solution

Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

<In the list are 113 DDR3 related pins and a pair of clock inputs>

=========================================================

I suspect the new quad spi flash pins cause some conflict and make Vivado to unplace those DDR3 pins. DDR3 constraints is specified inside DDR3 xdc, generated by Vivado.

I appreciate any help.

Thanks,

TD

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Visitor
Visitor
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Registered: ‎08-17-2016

I found the root cause of my Implementation issue:

Somehow, my Vivado generated mig_ddr3 xdc file got messed up and cause this issue.

TD

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