AR# 70148

msqxl · ‎01-02-2018

set XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES=1

call C:\Xilinx\SDK\2017.4\bin\program_flash -f boot
.bin -fsbl fsbl.elf -offset 0 -flash_type qspi_single -blank_check -verify

****** Xilinx Program Flash
****** Program Flash v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:localhost:3121

WARNING: Failed to connect to hw_server at TCP:localhost:3121
Attempting to launch hw_server at TCP:localhost:3121

Connected to hw_server @ TCP:localhost:3121
Available targets and devices:
Target 0 : jsn-JTAG-HS1-210512180081
Device 0: jsn-JTAG-HS1-210512180081-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mrd->addr=0xF8000110, data=0x00177EA0 =====
===== mwr->addr=0xF8000110, data=0x00177EA0 =====
MASKWRITE: addr=0xF8000110, mask=0x003FFFF0, newData=0x00177EA0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
===== mwr->addr=0xF8000100, data=0x0001A008 =====
MASKWRITE: addr=0xF8000100, mask=0x0007F000, newData=0x0001A008
===== mrd->addr=0xF8000100, data=0x0001A008 =====
===== mwr->addr=0xF8000100, data=0x0001A010 =====
MASKWRITE: addr=0xF8000100, mask=0x00000018, newData=0x0001A010
===== mrd->addr=0xF8000100, data=0x0001A010 =====
===== mwr->addr=0xF8000100, data=0x0001A011 =====
MASKWRITE: addr=0xF8000100, mask=0x00000001, newData=0x0001A011
===== mrd->addr=0xF8000100, data=0x0001A011 =====
===== mwr->addr=0xF8000100, data=0x0001A010 =====
MASKWRITE: addr=0xF8000100, mask=0x00000001, newData=0x0001A010
===== mrd->addr=0xF800010C, data=0x0000003F =====
READ: addr=0xF800010C, Data=0x0000003F
===== mrd->addr=0xF8000100, data=0x0001A010 =====
===== mwr->addr=0xF8000100, data=0x0001A000 =====
MASKWRITE: addr=0xF8000100, mask=0x00000010, newData=0x0001A000
===== mrd->addr=0xF8000120, data=0x1F000400 =====
===== mwr->addr=0xF8000120, data=0x1F000400 =====
MASKWRITE: addr=0xF8000120, mask=0x1F003F30, newData=0x1F000400
===== mrd->addr=0xF8000118, data=0x00177EA0 =====
===== mwr->addr=0xF8000118, data=0x00177EA0 =====
MASKWRITE: addr=0xF8000118, mask=0x003FFFF0, newData=0x00177EA0
===== mrd->addr=0xF8000108, data=0x0001A008 =====
===== mwr->addr=0xF8000108, data=0x0001A008 =====
MASKWRITE: addr=0xF8000108, mask=0x0007F000, newData=0x0001A008
===== mrd->addr=0xF8000108, data=0x0001A008 =====
===== mwr->addr=0xF8000108, data=0x0001A010 =====
MASKWRITE: addr=0xF8000108, mask=0x00000018, newData=0x0001A010
===== mrd->addr=0xF8000108, data=0x0001A010 =====
===== mwr->addr=0xF8000108, data=0x0001A011 =====
MASKWRITE: addr=0xF8000108, mask=0x00000001, newData=0x0001A011
===== mrd->addr=0xF8000108, data=0x0001A011 =====
===== mwr->addr=0xF8000108, data=0x0001A010 =====
MASKWRITE: addr=0xF8000108, mask=0x00000001, newData=0x0001A010
===== mrd->addr=0xF800010C, data=0x0000003F =====
READ: addr=0xF800010C, Data=0x0000003F
===== mrd->addr=0xF8000108, data=0x0001A010 =====
===== mwr->addr=0xF8000108, data=0x0001A000 =====
MASKWRITE: addr=0xF8000108, mask=0x00000010, newData=0x0001A000
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B

U-Boot 2017.01-00148-g4c61f9b-dirty (Sep 22 2017 - 09:50:06 -0600), Build: jenki
ns-mini_uboot-mini_uboot-218

Model: Zynq CSE QSPI Board
Board: Xilinx Zynq
DRAM: ECC disabled 256 KiB
WARNING: Caches not enabled
Using default environment

In: dcc
Out: dcc
Err: dcc
Model: Zynq CSE QSPI Board
Board: Xilinx Zynq
Zynq> sf probe 0 0 0
SF: unrecognized JEDEC id bytes: 00, 00, 00
Failed to initialize SPI flash at 0:0 (error -2)
Zynq> Sector size = 0.
f probe 0 0 0
Performing Erase Operation...
sf erase 0 220000
No SPI flash selected. Please run `sf probe'
Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Blank Check Operation...
0%...sf read FFFC0000 0 10000
No SPI flash selected. Please run `sf probe'
Zynq> cmp.b FFFC0000 FFFD0000 10000
byte at 0xfffc0000 (0xb8) != byte at 0xfffd0000 (0xff)
Total of 0 byte(s) were the same
Zynq> INFO: [Xicom 50-44] Elapsed time = 0 sec.
Blank Check Operation unsuccessful. The part is not blank.

ERROR: Flash Operation Failed

mkzo_brj · ‎01-03-2018

Hi,

Yes, it's still broken in 2017.4

The last working version was 2017.2, then Xilinx changed something in 2017.3 so that FSBL image has to be specified for flashing, apparently to make the process unified with the Ultrascale, and since then SPI flashing doesn't work anymore. Could someone from Xilinx debug this? Already a number of people reported this issue.

Cheers,

Marcin

msqxl · ‎01-03-2018

AR# 70148

2017.3 Zynq-7000 AP SoC: QSPI flash programming now requires that you specify an FSBL

https://china.xilinx.com/support/answers/70148.html

but I how to do ? I don't know how to do

glena · ‎01-04-2018

Maybe AR70148 will help.

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msqxl · ‎01-04-2018

According to AR# 70148 to do, still can't burn the flash，Please give more detailed solution

glena · ‎01-05-2018

Why is your FSBL running multiple times? It should only run once. What is your QSPI device? It is not being detected by SF Probe.

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msqxl · ‎01-07-2018

Because I tried many times.

QSPI flash is W25Q256 and N25Q128,Can burn in vivado SDK 2015.4 write success

I use vivado SDK 2017.4 try many times, can't succeed

Below is the 2015.4 log

U-Boot 2015.04-00002-g1777363 (Aug 21 2015 - 12:21:42)

Board: Xilinx Zynq
I2C: ready
DRAM: ECC disabled 256 KiB
WARNING: Caches not enabled
Using default environment

In: serial
Out: serial
Err: serial
Board: Xilinx Zynq
zynq-uboot> sf probe 0 0 0

SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
zynq-uboot> Sector size = 65536.
SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Performing Erase Operation...
sf erase 0 370000

SF: 3604480 bytes @ 0x0 Erased: OK
zynq-uboot> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 15 sec.
Performing Blank Check Operation...
0%...sf read FFFC0000 0 10000

SF: 65536 bytes @ 0x0 Read: OK
zynq-uboot> .......cmp.b FFFC0000 FFFD0000 10000

Total of 65536 byte(s) were the same
zynq-uboot> sf read FFFC0000 10000 10000

SF: 65536 bytes @ 0x10000 Read: OK

.

Total of 65536 byte(s) were the same
zynq-uboot> 100%
sf read FFFC0000 360000 A8E0

SF: 43232 bytes @ 0x360000 Read: OK
zynq-uboot> .....cmp.b FFFC0000 FFFD0000 A8E0

Total of 43232 byte(s) were the same
zynq-uboot> INFO: [Xicom 50-44] Elapsed time = 108 sec.
Verify Operation successful.

Flash Operation Successful

glena · ‎01-08-2018

It looks like SF Probe is not reading the JEDEC ID correctly in 2017.4. I'm talking with Development on this. Can you try to manually program your QSPI device with u-Boot? This is documented in page 50 of UG973.

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msqxl · ‎01-08-2018

Under uboot QSPI flash can be recognized, can erase, program。

ibaie · ‎01-10-2018

Hi @msqxl

Are you using the same FSBL for both Flash programming from SDK and for booting U-Boot (which is detecting/reading/writing properly the flash device)? Please ensure on this point as that way you can discard issues in the PS configuration side. Get the logs and check the compilation timestamps.

Would be also good to use the same FSBL binary (generated in 2017.4) with SDK 2015.4 program_flash. This way we can check if the issue is in the mini-uboot image used by the program_flash tool.

Regards

Ibai

Ibai
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msqxl · ‎01-10-2018

yes,program_flash and uboot use the same FSBL.

SDK 2015.4 program_flash don't need FSBL。

SDK 2017.4 program_flash use FSBL generated by the SDK 2015.4, also won't work

ibaie · ‎01-11-2018

Hi @msqxl

If the same FSBL is working to load U-Boot and access to the Flash device, I will recommend you to use a hardware probe to check the QSPI interface during the program_flash usage. As you can see in the boot log, the JEDEC ID that the mini u-boot gets from the target is not valid, so you need to check what's goes wrong in the transaction.

Just for loging purposes would be great if you could post the the log of "sf probe 0 0 0" command when you launch U-Boot (including the FSBL timestamp as well).

Regards

Ibai

Ibai
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msqxl · ‎01-11-2018

Why don't you try? zc702、zc706 development board use SDK 2017.4 ,can erase QSPI Flash ? erase , erase,erase

ibaie · ‎01-18-2018

Hi @msqxl

I just tested SDK 2017.4 with my ZC702 board and I was able to program the flash succesfully. As you can see in both logs (SDK log and console output), the FSBL is based on 2017.4 release and mini-uboot as well.

****** Xilinx Program Flash
****** Program Flash v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ tcp:149.199.166.134:3121

Connected to hw_server @ tcp:149.199.166.134:3121
Available targets and devices:
Target 0 : jsn-XSC0-AAo1BIJd0
        Device 0: jsn-XSC0-AAo1BIJd0-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mrd->addr=0xF8000110, data=0x00177EA0 =====
===== mwr->addr=0xF8000110, data=0x00177EA0 =====
MASKWRITE: addr=0xF8000110, mask=0x003FFFF0, newData=0x00177EA0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
===== mwr->addr=0xF8000100, data=0x0001A008 =====
MASKWRITE: addr=0xF8000100, mask=0x0007F000, newData=0x0001A008
===== mrd->addr=0xF8000100, data=0x0001A008 =====
===== mwr->addr=0xF8000100, data=0x0001A010 =====
MASKWRITE: addr=0xF8000100, mask=0x00000018, newData=0x0001A010
===== mrd->addr=0xF8000100, data=0x0001A010 =====
===== mwr->addr=0xF8000100, data=0x0001A011 =====
MASKWRITE: addr=0xF8000100, mask=0x00000001, newData=0x0001A011
===== mrd->addr=0xF8000100, data=0x0001A011 =====
===== mwr->addr=0xF8000100, data=0x0001A010 =====
MASKWRITE: addr=0xF8000100, mask=0x00000001, newData=0x0001A010
===== mrd->addr=0xF800010C, data=0x0000003F =====
READ: addr=0xF800010C, Data=0x0000003F
===== mrd->addr=0xF8000100, data=0x0001A010 =====
===== mwr->addr=0xF8000100, data=0x0001A000 =====
MASKWRITE: addr=0xF8000100, mask=0x00000010, newData=0x0001A000
===== mrd->addr=0xF8000120, data=0x1F000400 =====
===== mwr->addr=0xF8000120, data=0x1F000400 =====
MASKWRITE: addr=0xF8000120, mask=0x1F003F30, newData=0x1F000400
===== mrd->addr=0xF8000118, data=0x00177EA0 =====
===== mwr->addr=0xF8000118, data=0x00177EA0 =====
MASKWRITE: addr=0xF8000118, mask=0x003FFFF0, newData=0x00177EA0
===== mrd->addr=0xF8000108, data=0x0001A008 =====
===== mwr->addr=0xF8000108, data=0x0001A008 =====
MASKWRITE: addr=0xF8000108, mask=0x0007F000, newData=0x0001A008
===== mrd->addr=0xF8000108, data=0x0001A008 =====
===== mwr->addr=0xF8000108, data=0x0001A010 =====
MASKWRITE: addr=0xF8000108, mask=0x00000018, newData=0x0001A010
===== mrd->addr=0xF8000108, data=0x0001A010 =====
===== mwr->addr=0xF8000108, data=0x0001A011 =====
MASKWRITE: addr=0xF8000108, mask=0x00000001, newData=0x0001A011
===== mrd->addr=0xF8000108, data=0x0001A011 =====
===== mwr->addr=0xF8000108, data=0x0001A010 =====
MASKWRITE: addr=0xF8000108, mask=0x00000001, newData=0x0001A010
===== mrd->addr=0xF800010C, data=0x0000003F =====
READ: addr=0xF800010C, Data=0x0000003F
===== mrd->addr=0xF8000108, data=0x0001A010 =====
===== mwr->addr=0xF8000108, data=0x0001A000 =====
MASKWRITE: addr=0xF8000108, mask=0x00000010, newData=0x0001A000
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B


U-Boot 2017.01-00148-g4c61f9b-dirty (Sep 22 2017 - 09:50:06 -0600), Build: jenkins-mini_uboot-mini_uboot-218

Model: Zynq CSE QSPI Board
Board: Xilinx Zynq
DRAM:  ECC disabled 256 KiB
WARNING: Caches not enabled
Using default environment

In:    dcc
Out:   dcc
Err:   dcc
Model: Zynq CSE QSPI Board
Board: Xilinx Zynq
Zynq> sf probe 0 0 0
SF: Detected n25q128a with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Zynq> Sector size = 65536.
f probe 0 0 0
Performing Erase Operation...
sf erase 0 20000
SF: 131072 bytes @ 0x0 Erased: OK
Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Blank Check Operation...
0%...sf read FFFC0000 0 10000
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Read: OK
Zynq> cmp.b FFFC0000 FFFD0000 10000
Total of 65536 byte(s) were the same
Zynq> 100%
sf read FFFC0000 10000 9708
device 0 offset 0x10000, size 0x9708
SF: 38664 bytes @ 0x10000 Read: OK
Zynq> cmp.b FFFC0000 FFFD0000 9708
Total of 38664 byte(s) were the same
Zynq> INFO: [Xicom 50-44] Elapsed time = 1 sec.
Blank Check Operation successful. The part is blank.
Performing Program Operation...
0%...sf write FFFC0000 0 19708
device 0 offset 0x0, size 0x19708
SF: 104200 bytes @ 0x0 Written: OK
Zynq> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 1 sec.
Performing Verify Operation...
sf read FFFC0000 0 10000
device 0 offset 0x0, size 0x10000
SF: 65536 bytes @ 0x0 Read: OK
Zynq> cmp.b FFFC0000 FFFD0000 10000
Total of 65536 byte(s) were the same
Zynq> 100%
sf read FFFC0000 10000 9708
device 0 offset 0x10000, size 0x9708
SF: 38664 bytes @ 0x10000 Read: OK
Zynq> cmp.b FFFC0000 FFFD0000 9708
Total of 38664 byte(s) were the same
Zynq> INFO: [Xicom 50-44] Elapsed time = 0 sec.
Verify Operation successful.

Flash Operation Successful

Xilinx First Stage Boot Loader
Release 2017.4  Jan 18 2018-03:20:39
Devcfg driver initialized
Silicon Version 3.1
Boot mode is JTAG

I would recommend you to use an osciloscope to check what's going wrong in the QSPI interface, as it seems that sf probe is not getting the right JEDEC ID.

Regards,

Ibai

Ibai
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te7a · ‎01-20-2018

I'm having the exact same problem,

after upgrading from 2017.2 to 2017.4, I can't flash the QSPI from SDK anymore, I'm using 706 board and I build my project with 2 configurations, one with DDR and another one without DDR and FSBL in XIP mode.

in 2017.2 I can flash both projects on the board with the dip switches configured in either QSPI or JTAG modes.

in 2017.4 I can flash ONLY the project with DDR and ONLY when dip switches are in JTAG mode.

Here is the error I get in 2017.4:

****** Xilinx Program Flash
****** Program Flash v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:127.0.0.1:3121

WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-SMT2-210251A013AD
Device 0: jsn-JTAG-SMT2-210251A013AD-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
Problem in Initializing Hardware
Flash programming initialization failed.

ERROR: Flash Operation Failed

te7a · ‎01-20-2018

and here is the error when switches are in JTAG boot mode:

****** Xilinx Program Flash
****** Program Flash v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:127.0.0.1:3121

WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-SMT2-210251A013AD
Device 0: jsn-JTAG-SMT2-210251A013AD-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
BOOT_MODE REG = 0x00000000
Problem in Initializing Hardware
Flash programming initialization failed.

ERROR: Flash Operation Failed

te7a · ‎01-20-2018

and for the same board, same image but using 2017.2, it works

****** Xilinx Program Flash
****** Program Flash v2017.2 (64-bit)
**** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:127.0.0.1:3121

WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-SMT2-210251A013AD
Device 0: jsn-JTAG-SMT2-210251A013AD-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
BOOT_MODE REG = 0x00000001
WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
f probe 0 0 0
Performing Erase Operation...
Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 16 sec.
Performing Program Operation...
0%...10%...20%...30%...40%...50%...60%...70%...80%...90%...100%
Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 64 sec.

Flash Operation Successful

jiv4ik · ‎01-26-2018

I have same problem whith same logs.

But I can program QSPI Flash in Vivado tool through Hardware manager (with PSMODE[3:0] = 0000'b)

aschweiz · ‎03-12-2018

Exactly the same issue here.

Neither AR70148 nor AR70310 fixed it.

Connected to hw_server @ TCP:localhost:3121

Available targets and devices:

Target 0 : jsn-Zed-210248774385

Device 0: jsn-Zed-210248774385-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory

BOOT_MODE REG = 0x00000000

f probe 0 0 0

Performing Erase Operation...

Erase Operation successful.

INFO: [Xicom 50-44] Elapsed time = 0 sec.

Performing Blank Check Operation...

0%...INFO: [Xicom 50-44] Elapsed time = 1 sec.

Blank Check Operation unsuccessful. The part is not blank.

ERROR: Flash Operation Failed

glena · ‎03-12-2018

@aschweiz To add expanded debug log for program flash, please use

XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES = 1

have you also tried adding this environment variable?

XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ = 10000000

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aschweiz · ‎03-12-2018

@glena I've added the two environment variables. It still doesn't work.

Attached is the output from program_flash.

aschweiz · ‎03-12-2018

sorry, forget it -

it's actually working for me now.

I've interrupted it because I thought it was in an infinite loop, but it was just very slow, probably because of the debug output.

Thanks!

tmauney · ‎05-21-2018

What is the FLASH_BASE_ADDRESS for the ZC702 for SDK 2017.2

Or where can I find it ? I've tried 0xFC000000 and 0xF8000000

I get an error (113) when calling the following function using either address.

/*
* Initialize the Flash Library.
*/
Status = XFlash_Initialize(&FlashInstance, FLASH_BASE_ADDRESS, FLASH_MEM_WIDTH, 0);

betontalpfa · ‎02-07-2020

Same issue here, with ZedBoard.

Everithing is OK when I use Out Of Box SD Card image. I can program the QSPI flash, in both JTAG and QSPI mode.
I designed a somple "led-blink" design, which works if I start from SDK (launch on hardware...) (I with or without DDR)
I've generated an FSBL (default FSBL for my hardware), I've created a BOOT image, but the Flash programming, failed, with Blank Check Operation unsuccessful. The part is not blank.
If I use the FSBL from the Out Of Box SD Card Image, with the previously generaed BOOT image (the BOOT image contains the generated image), the flash programming is successful, but only in JTAG mode. (The QSPI mode fails)

My goal is to program a:

Custom Board (with Zynq device), (but first I want to work with this Zed-board)
No-DDR
SPI-mode

I use:

ZedBoard (xc7z020clg484-1)
Vivado/SDK 2017.4
Win 10

Can't Program Flash on zynq use Vivado 2017.4 but 2015.4 is OK

AR# 70148

2017.3 Zynq-7000 AP SoC: QSPI flash programming now requires that you specify an FSBL