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Observer
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Registered: ‎04-23-2018

Can't program QSPI Flash, no DDR

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xc7z020clg400-2, Vivado/SDK 2017.4. I've been following this: http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip, as well as this post: https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/Can-t-flash-QSPI/td-p/813536. I'm able to directly write and read the flash using the xqspips_g128_flash_example, so I know that it isn't a connection issue. We are using a Spansion S25FL256L, as a our flash chip which I know isn't directly compatible, however it is identified by Vivado as the Spansion S25FL256S (which is a compatible chip). Any help at this point is appreciated. I've attempted to program flash in 2016.4 without luck, and decided to install 2017.4 in order to see if the two examples above would work, which they don't. This is the output when I run the "Program Flash" utility in SDK:

 

****** Xilinx Program Flash
****** Program Flash v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

Connecting to hw_server @ TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn1
Target 1 : jsn-DLC10-000017df129e01
Target 2 : jsn2
Device 0: jsn-DLC10-000017df129e01-4ba00477-0
Device 1: jsn-DLC10-000017df129e01-23727093-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mrd->addr=0xF8000110, data=0x00177EA0 =====
===== mwr->addr=0xF8000110, data=0x00177EA0 =====
MASKWRITE: addr=0xF8000110, mask=0x003FFFF0, newData=0x00177EA0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
===== mwr->addr=0xF8000100, data=0x0001A008 =====
MASKWRITE: addr=0xF8000100, mask=0x0007F000, newData=0x0001A008
===== mrd->addr=0xF8000100, data=0x0001A008 =====
===== mwr->addr=0xF8000100, data=0x0001A010 =====
MASKWRITE: addr=0xF8000100, mask=0x00000018, newData=0x0001A010
===== mrd->addr=0xF8000100, data=0x0001A010 =====
===== mwr->addr=0xF8000100, data=0x0001A011 =====
MASKWRITE: addr=0xF8000100, mask=0x00000001, newData=0x0001A011
===== mrd->addr=0xF8000100, data=0x0001A011 =====
===== mwr->addr=0xF8000100, data=0x0001A010 =====
MASKWRITE: addr=0xF8000100, mask=0x00000001, newData=0x0001A010
===== mrd->addr=0xF800010C, data=0x0000003F =====
READ: addr=0xF800010C, Data=0x0000003F
===== mrd->addr=0xF8000100, data=0x0001A010 =====
===== mwr->addr=0xF8000100, data=0x0001A000 =====
MASKWRITE: addr=0xF8000100, mask=0x00000010, newData=0x0001A000
===== mrd->addr=0xF8000120, data=0x1F000400 =====
===== mwr->addr=0xF8000120, data=0x1F000400 =====
MASKWRITE: addr=0xF8000120, mask=0x1F003F30, newData=0x1F000400
===== mrd->addr=0xF8000118, data=0x00177EA0 =====
===== mwr->addr=0xF8000118, data=0x00177EA0 =====
MASKWRITE: addr=0xF8000118, mask=0x003FFFF0, newData=0x00177EA0
===== mrd->addr=0xF8000108, data=0x0001A008 =====
===== mwr->addr=0xF8000108, data=0x0001A008 =====
MASKWRITE: addr=0xF8000108, mask=0x0007F000, newData=0x0001A008
===== mrd->addr=0xF8000108, data=0x0001A008 =====
===== mwr->addr=0xF8000108, data=0x0001A010 =====
MASKWRITE: addr=0xF8000108, mask=0x00000018, newData=0x0001A010
===== mrd->addr=0xF8000108, data=0x0001A010 =====
===== mwr->addr=0xF8000108, data=0x0001A011 =====
MASKWRITE: addr=0xF8000108, mask=0x00000001, newData=0x0001A011
===== mrd->addr=0xF8000108, data=0x0001A011 =====
===== mwr->addr=0xF8000108, data=0x0001A010 =====
MASKWRITE: addr=0xF8000108, mask=0x00000001, newData=0x0001A010
===== mrd->addr=0xF800010C, data=0x0000003F =====
READ: addr=0xF800010C, Data=0x0000003F
===== mrd->addr=0xF8000108, data=0x0001A010 =====
===== mwr->addr=0xF8000108, data=0x0001A000 =====
MASKWRITE: addr=0xF8000108, mask=0x00000010, newData=0x0001A000
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B

 


U-Boot 2017.01-00148-g4c61f9b-dirty (Sep 22 2017 - 09:50:06 -0600), Build: jenkins-mini_uboot-mini_uboot-218

 

Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

DRAM: ECC disabled 256 KiB

WARNING: Caches not enabled

Using default environment

 

In: dcc

Out: dcc

Err: dcc

Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Zynq> sf probe 0 10000000 0


SF: unrecognized JEDEC id bytes: 01, 60, 19

Failed to initialize SPI flash at 0:0 (error -2)

Zynq> Sector size = 0.
f probe 0 10000000 0


Performing Erase Operation...
sf erase 0 5E0000


No SPI flash selected. Please run `sf probe'

Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 0 sec.
Performing Program Operation...
0%...sf write FFFC0000 0 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 20000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 40000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 60000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 80000 20000


No SPI flash selected. Please run `sf probe'

Zynq> 10%...sf write FFFC0000 A0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 C0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 E0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 100000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 120000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 140000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 160000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 180000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 1A0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> 30%...sf write FFFC0000 1C0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 1E0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 200000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 220000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 240000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 260000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 280000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 2A0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 2C0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> 50%...sf write FFFC0000 2E0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 300000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 320000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 340000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 360000 20000


No SPI flash selected. Please run `sf probe'

Zynq> 60%...sf write FFFC0000 380000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 3A0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 3C0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 3E0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 400000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 420000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 440000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 460000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 480000 20000


No SPI flash selected. Please run `sf probe'

Zynq> 80%...sf write FFFC0000 4A0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 4C0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 4E0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 500000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 520000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 540000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 560000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 580000 20000


No SPI flash selected. Please run `sf probe'

Zynq> sf write FFFC0000 5A0000 20000


No SPI flash selected. Please run `sf probe'

Zynq> 100%
sf write FFFC0000 5C0000 1BB00


No SPI flash selected. Please run `sf probe'

Zynq> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 96 sec.
Performing Verify Operation...
0%...sf read FFFC0000 0 10000


No SPI flash selected. Please run `sf probe'

Zynq> cmp.b FFFC0000 FFFD0000 10000


byte at 0xfffc0000 (0x0) != byte at 0xfffd0000 (0xfe)

Total of 0 byte(s) were the same

Zynq> INFO: [Xicom 50-44] Elapsed time = 1 sec.
Verify Operation unsuccessful.

ERROR: Flash Operation Failed

 

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Moderator
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Registered: ‎03-19-2014

Re: Can't program QSPI Flash, no DDR

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In the case without DDR, you'll want to build the Zynq_cse_qspi platform wiki u-Boot.   There may be some system specific edits you will need to make from there.

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Observer
Observer
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Registered: ‎04-23-2018

Re: Can't program QSPI Flash, no DDR

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Also, I have the Environment Variables set: XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ = 10000000, and XIL_CSE_ZYNQ_DISPLAY_UBOOT_MESSAGES = 1. XIP_mode, and Standalone OS.

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Registered: ‎03-19-2014

Re: Can't program QSPI Flash, no DDR

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Can you try this in 2018.1? 

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Registered: ‎04-23-2018

Re: Can't program QSPI Flash, no DDR

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Haven't tried 2018.1, are there any updates regarding programming flash in this version of SDK?

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Registered: ‎03-19-2014

Re: Can't program QSPI Flash, no DDR

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Yes, 2018.1 uses a new mini uBoot, the  XIL_CSE_ZYNQ_UBOOT_QSPI_FREQ_HZ = 10000000 env variable is no longer necessary.

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Observer
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Registered: ‎04-23-2018

Re: Can't program QSPI Flash, no DDR

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I'll try this. Will update after.

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Observer
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Registered: ‎04-23-2018

Re: Can't program QSPI Flash, no DDR

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Using 2018.1 didn't make a difference. I also attempted to change the spi.cfg and modify the S25FL256S to be the IDCODE that corresponds to my flash, 01 60 19, but it seems that modifying this file didn't change anything. Is there any way to trick the tools into believing that my IDCODE corresponds to a known device?

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Registered: ‎03-19-2014

Re: Can't program QSPI Flash, no DDR

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please post the programming log.   In the sf probe command, is your QSPI device found?

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Registered: ‎03-19-2014

Re: Can't program QSPI Flash, no DDR

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I'm sorry, I missed the comment that you are not using a supported QSPI device.  You'll need to program your QSPI manually via uBoot.   You can refer to AR62743 for how to attempt to program unsupported QSPI devices

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Re: Can't program QSPI Flash, no DDR

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Does that mean that we need to build u-boot manually? Is there any other way to gain access to the sf_params.c and add our device?

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Re: Can't program QSPI Flash, no DDR

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You can try one of the pre-built uBoots at Wiki_Zynq+Releases

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Re: Can't program QSPI Flash, no DDR

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Ours is a custom board, so I would need to modify the pre-built image. But this isn't possible with the bin and elf files that are given. Or is it? Sorry pretty new to this stuff.

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Re: Can't program QSPI Flash, no DDR

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The .bin and .elf files are compiled, so you will need to modify uBoot.    First verify your QSPI device is compatible with the Zynq BootROM using the example in AR62743.   You may need to contact Spansion  to see if your device aliases to a supported JEDEC id.

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Re: Can't program QSPI Flash, no DDR

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I've been attempting to build u-boot and when I do make inside the uboot directory, after make zynq_zc702_defconfig, it fails due to bad value (armv5) for -march= switch. Not sure how to get around this. This is using the uboot from git as well as the newest dtc.

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Re: Can't program QSPI Flash, no DDR

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Which tagged version of uBoot are you using?

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Re: Can't program QSPI Flash, no DDR

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Not sure how to check that, but it's the latest one on the Xilinx u-boot GitHub. edit: 2018.1

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Re: Can't program QSPI Flash, no DDR

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When you download, check the branch.   Don't use the Master, use a tagged branch to match the tool chain version you are using.

 

uboot_tag.JPG

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Re: Can't program QSPI Flash, no DDR

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2018.1

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Re: Can't program QSPI Flash, no DDR

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After including CROSS_COMPILE=arm-none-eabi- when I build u-boot, I now receive the message: *** Your GCC is older than 6.0 and is not supported. I checked the version of arm-none-eabi-gcc and it says:

arm-none-eabi-gcc (Linaro GCC 7.2-2017.11-rc1) 7.2.1 20171011
Copyright (C) 2017 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

 

My normal gcc is version 6.4.0-17ubuntu1~16.04. Not sure where to go from here.

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Re: Can't program QSPI Flash, no DDR

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I was able to produce a u-boot.elf. Now what do I do? How can I use what was produced to program the flash?

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Re: Can't program QSPI Flash, no DDR

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Go to this wiki page http://www.wiki.xilinx.com/Programming+QSPI+from+U-boot+ZC702

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Re: Can't program QSPI Flash, no DDR

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Will this still work without ddr?

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Re: Can't program QSPI Flash, no DDR

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Because I tried the u-boot approach, and wanted to dow my mcs file into the QSPI linear address (0xfc000000) and it says that QSPI is disabled. And all the examples I've seen dow the bin/mcs file into the ddr address (0x08000000).

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Re: Can't program QSPI Flash, no DDR

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In the case without DDR, you'll want to build the Zynq_cse_qspi platform wiki u-Boot.   There may be some system specific edits you will need to make from there.

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Explorer
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Registered: ‎10-12-2018

Re: Can't program QSPI Flash, no DDR

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I know that this thread has already solved, but I can suggest

zynq_flash project for erase/write/read QSPI flash of Zynq devices.

In this case the FSBL/Uboot wont be used during the flashing, which makes FSBL simpler.

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