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jt94096
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Registered: ‎09-21-2018

PL not programmed after launching debug in Vitis

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I'm seeing odd behavior on a Trenz carrier + FPGA module (which has a Zynq US+ MPSoC) where the PL is not operational after launching debug in Vitis but if I subsequently program the PL from Vivado or Vitis  then it starts working. I have been following the same process with a ZCU106 and do not have this issue (launch debug, Vitis programs FPGA/PL, run software, open HW Manager in Vivado to use ILAs, see PL I/O toggling, etc).

My debug configuration has default/pre-filled values, including programming the FPGA. When I launch debug I see the progress bar as it programs the FPGA. The PL design just uses a clock from the PS to toggle some outputs, but I see no activity (or debug hub). If I program the FPGA (i.e. PL) again (as software is still running) then the outputs toggle as expected and I see the debug hub. This works if I program the PL from Vivado or Vitis. It either does not actually program the PL or somehow clears it afterwards.

If I program the QSPI flash then my application boots and runs at powerup but I still don't see any PL activity.

Thanks for any suggestions.

Jason

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denist
Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

I would check if DONE goes high (with a scope) for a brief time. If so maybe there's no enough power for the PL to operate?

Also, if you boot from QSPI with FSBL debug prints, I would like to see if there's any error reported there.

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denist
Xilinx Employee
Xilinx Employee
256 Views
Registered: ‎10-11-2011

I would check if DONE goes high (with a scope) for a brief time. If so maybe there's no enough power for the PL to operate?

Also, if you boot from QSPI with FSBL debug prints, I would like to see if there's any error reported there.

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jt94096
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Registered: ‎09-21-2018

Thanks denist, I have been debugging other aspects of the chip and tool behavior and I can now program the PL ok just by launching a debug session so I am going to close this.

 

Jason

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