01-28-2019 03:50 AM
For reference we intend to support the 030, 035 and 045 devices.
Would the following be practical please ? :-
We store our program in the first 'page' of flash memory i.e. with the extended address register and zero and our bitstream in the second page. We could then switch the extended address register to zero after configuring the fabric thereby removing the need for the workaround mentioned in AR# 57744 (Design Advisory for Zynq-7000 SoC - Zynq and QSPI reset requirements when using larger than 16MB flash).
If a soft reset were to occur during code execution we would, I assume, restart with the first page of flash thereby booting normally.
I know this might seem wasteful but we have 64MB.
02-01-2019 03:18 PM
To be 100% recovery on the reset without a reset going to the flash you should copy the FSBL at every 16MB (or 32MB if you are Dual Parallel) boundary.
Is that what you are proposing?
If not, you might have a window in time where, if a reset is receive, the part will be trying to boot from the sencond page NOT finding the image.
If you can guarantee that no reset is received during that time, then swithing back to the first page after bitstream programming should work fine.
06-12-2019 01:23 PM
Have you been able to test and verify this solution to AR# 57744?
We are designing a board and 4KB of memory lost to the duplication of first stage boot loader code at 16MB boundaries seems preferable to the additional CPLD hardware and bitfile overhead of the orriginally proposed solution.
Have you experienced any other issues with implementing this work around?
06-13-2019 03:51 PM
I am pretty sure the duplication of FSBL at every boundary works.
You could try it on the Avnet ZED board if you want to be 110% sure. There's a 32MB flash in there.