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Observer josephchau77
Observer
986 Views
Registered: ‎09-16-2018

Run two Core using share memory on Zynq Ultrascale+

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Hello

 

I try to run 2 Bare-metal application (no Linux involved) each no GPU_53_0 and RPU_5_0 respectively using share memory

for example RPU_5_0 send a serial of number 1234 into a common memory (share by both cores) then APU_53_0 will

goto share memory and get that content (i.e. 1234) then display the value to the console.   Any one have this information

or know how to implement this task please pass along to me.

Your help is greatly appreciated

 

Regards

joe chau

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Observer josephchau77
Observer
933 Views
Registered: ‎09-16-2018

Re: Run two Core using share memory on Zynq Ultrascale+

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Thanks

This task is simple just find out which memory is visible by both cores of 

the CPU then use that to transfer data between two core.

I did found out and solved this issue already

 

Best regards

Joe

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Xilinx Employee
Xilinx Employee
942 Views
Registered: ‎10-11-2011

Re: Run two Core using share memory on Zynq Ultrascale+

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Do you need large memory regions or just passing few bytes of messaging?

If you are looking for messages between eh two core you should be leveraging the IPI (Inter Processor Interrupts).

There is a good standalone example in the SDK installation folder (look for the ipipsu folder)

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Observer josephchau77
Observer
934 Views
Registered: ‎09-16-2018

Re: Run two Core using share memory on Zynq Ultrascale+

Jump to solution

Thanks

This task is simple just find out which memory is visible by both cores of 

the CPU then use that to transfer data between two core.

I did found out and solved this issue already

 

Best regards

Joe

View solution in original post

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Visitor jostmp
Visitor
226 Views
Registered: ‎08-21-2019

Re: Run two Core using share memory on Zynq Ultrascale+

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I know this is an old thread but i am doing a similar task.

"This task is simple just find out which memory is visible by both cores of the CPU"

where did you find the memory map showing the shared memory regions?

mJ

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Visitor jostmp
Visitor
195 Views
Registered: ‎08-21-2019

Re: Run two Core using share memory on Zynq Ultrascale+

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NM, the data is in the TRM. Just declare a DDR address outside the range used by the processors for the shared mem  and Disable cache or flush and invalidate.