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marcoventurini
Adventurer
Adventurer
359 Views
Registered: ‎10-02-2014

XC7Z020 does not boot if PS_SRST_B is asserted at power on

Hello,

We have several product featuring the XC7Z020 chip, we are now investigating a problem where, sometimes, the FPGA fails to boot.

After looking at the power on sequence we found that this happens always when PS_SRST_B is held asserted during the power on sequence.

We have a button connected to this reset, and if we keep the button pressed at the power on, when the button is released the FPGA fails to boot.

All the documentation I found is on the PS_POR_B that can accidentally trigger a "Secure Lockdown", but i could not find any recommendation about  PS_SRST_B.

Has anybody any clue about why this can be happening?

Thanks,

Marco

 

 

 

 

 

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4 Replies
katsuki
Xilinx Employee
Xilinx Employee
269 Views
Registered: ‎11-05-2019

Hi @marcoventurini 

The following post will be helpful. Purpose of PS_SRST_B

 

 

 

 


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marcoventurini
Adventurer
Adventurer
237 Views
Registered: ‎10-02-2014

Hello katsuki,

Thanks for your reply,
The post you linked is basically telling me that PS_SRST_B resets the system, and that's OK.

Let my clarify my situiation

I power on board with PS_SRST_B held LOW (asserted), and the zynq will not start booting, ans that's fine, this is what i expect too.

I deassert PS_SRST_B (HIGH) but the zynq does NOT start the boot process, and this is not the expected behavior.

Thanks again,

Marco

 

 

 

 

 

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katsuki
Xilinx Employee
Xilinx Employee
155 Views
Registered: ‎11-05-2019

Hi @marcoventurini 

Did you Assert and De-Assert POR_B?

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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marcoventurini
Adventurer
Adventurer
146 Views
Registered: ‎10-02-2014

I can do all the tests that I want, If i send a  POR_B afterward it will trigger an hard reset and the ZYNQ will boot, as expected, if I sent a PS_SRST_B instead, nothing happens.

If course this is not a viable solution since this is a poweron sequence driven only by passive components.

I already looked at the documents, but I could not find anything about it, maybe I have overlooked something, if you can point me out at the right document/chapter i can double check the boot sequence.

Thanks,

Marco

 

 

 

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