02-05-2019 03:25 AM
I've got a ZYNQ MPSoC US+ design with a PL SYSMON instantiated via the System Management Wizard (I'm using Vivado v2017.4), and I'm trying to program its eFuses in order to do a PUF registration operation.
I'm trying to follow the prescribed method given in XAPP1319, dumping information to the UART as I go, and using the example code provided by Xilinx. When I downloaded and executed the resulting program via the SDK (v2017.4) I noticed that it seemed to be hanging in XilSKey_ZynqMp_EfusePs_WritePufHelprData( ). Tracing through execution via the SDK debugger I find that it's stuck in XSysMonPsu_CfgInitialize( ) as it goes to read the PL_CTRL_STATUS register of the AMS (0xFF5A_0044) and finds that the accessible bit (bit 0) is always 0, which indicates that the PS cannot access the PL SYSMON registers.
I then went back, removed the instantiation of the PL SYSMON from the design, and then the aforementioned bit is a 1 and the program can continue execution. I've retried the flow by instantiating various permutations of the PL SYSMON (e.g., AXI interface, DRP interface, none w/DCLK, none w/o DCLK) using the System Management Wizard and in all cases PL_CTRL_STATUS is 0. It's only when I don't instantiate the PL SYSMON block that it is non-zero.
What am I missing here? I doubt very much that instantiating a PL SYSMON block prevents you from programming eFuses, so I must be doing something wrong, but I can't figure out what that is so I'm hoping one of the Xilinx experts can set me straight. Perhaps the example code isn't what I should be using, but if not, what is?
Any insight would be greatly appreciated. Thanks!
02-15-2019 03:08 PM
Are you using the puf_registration exampe?
I have to guess there's some interaction between the PS and the PL SysMon.
In my opinion when programming eFUSEs keep your design simple (maybe PS only) and don't use your full design which just add a lot of complexity to somethig already coplexed like eFUSE rpogramming.
02-18-2019 06:18 AM
I am indeed using the puf_registration example provided as sample code in the SDK.
I agree that there must be some interaction, I'm just trying to understand what that is, why it exists, and how to work around it as I'm not a fan of having to complexify the manufacturing process by requiring the use of multiple PL images to deal with an unexplained device issue.