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Participant lennart_mle
Participant
400 Views
Registered: ‎07-03-2018

Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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Hi there,

I'm having trouble to answer the following questions by reading the TRM. We are planning to use a fairly large dual parallel x8 QSPI Flash of 258MB. The question basically is: Can we only communicate with this flash in I/O mode or can we address the first 32MB in linear mode and than switch to I/O mode for the higher address reagions? 

We were hoping to use the execution-in-place (linear mode only) feature with this flash by placing the BOOT.BIN in the first 32MB. Once the FSBL and User application are done the u-boot will start to load the Petalinux kernel. The kernel and rootfs shall be placed somewhere above the 32MB boundary and therefore the u-boot would have to be configured to use I/O mode. 
Is this possible or is linear mode not available for QSPI flashes larger than 32MB at all? 

Thanks!

Lennart

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1 Solution

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Xilinx Employee
Xilinx Employee
277 Views
Registered: ‎10-11-2011

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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The issue is that different flash vendors handle the 16MB boundary (24-bit addressing) differently.

The bootROM makes the assumption that the flash access is linear BUT some of them actually "wrap-around" when crossing the boundary of 16MB.

NOTE: with 24-bit of address you can only address lineraly 16MB. You need to leverage the EAR to "change" the page on larger than 16MB flashes.

The SW can definetly be written to handle that but there are few gotchas (like the one described in that AR or the vendor specific way to handle the 16MB boundaries).

In my opininon keeping the XIP in 16MB and skipt the initial 32K is the safer approach.

6 Replies
Xilinx Employee
Xilinx Employee
339 Views
Registered: ‎10-11-2011

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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In zynq-7000 the bootROM uses linear mode and then FSBL switches to IO Mode for larger flashes, so what you are describing is possible.

There are few considerations while using larger than 16MB in zynq-7000. Look for ARs on the topic.

Participant lennart_mle
Participant
320 Views
Registered: ‎07-03-2018

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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Hi Denist,

grate! Thanks for the answer! IF you can point me to further AR's naming the limitations I would very happy. All I found so far was the limitation about the location of the BOOT.BIN (first 32MB but not the very first 32kB).

By the way. Do I the understand the sentence from AR 60803 correctly: "if QSPI boots with XIP, the first word is used to remap the flash linear address space". To me that means I can tell the BootRom an arbitrary location on where to find the BOOT.BIN? So the limitation of the the BOOT.BIN having to be placed in the first 32MB of the flash can be counteracted? Can I increase the address space as well so that I could place more than one or crazy large BOOT.BINs to the BootRom's area to read from in linear mode?

 

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Xilinx Employee
Xilinx Employee
303 Views
Registered: ‎10-11-2011

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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You are looking at the right AR.

I am not sure what "the first word is used to remap the flash linear address space" really means BUT I suggest this workaround:

"

Erase the first 32KB of flash and program the boot image at 0x0 + 32KB offset.
The BootROM will fail booting from 0x0, then will fallback and boot from 0x0 +32KB offset (see UG585 Zynq-7000-TRM for Boot Partition Search).

"

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Participant lennart_mle
Participant
287 Views
Registered: ‎07-03-2018

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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Hi denist,

thanks again. I saw the recommended Workaround in AR. "Workaround" sounds like there is a bug but I'd like to believe it is a feature? Remapping the linear address space to either get the full linear address space or even more than 32MB? 

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Xilinx Employee
Xilinx Employee
278 Views
Registered: ‎10-11-2011

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

Jump to solution

The issue is that different flash vendors handle the 16MB boundary (24-bit addressing) differently.

The bootROM makes the assumption that the flash access is linear BUT some of them actually "wrap-around" when crossing the boundary of 16MB.

NOTE: with 24-bit of address you can only address lineraly 16MB. You need to leverage the EAR to "change" the page on larger than 16MB flashes.

The SW can definetly be written to handle that but there are few gotchas (like the one described in that AR or the vendor specific way to handle the 16MB boundaries).

In my opininon keeping the XIP in 16MB and skipt the initial 32K is the safer approach.

Participant lennart_mle
Participant
261 Views
Registered: ‎07-03-2018

Re: Zynq 7000 switch from linear mode to I/O mode once FSBL is done

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Alright I think now I understand. Thanks for taking the time to explain!

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