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siddhantmodi
Visitor
Visitor
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Registered: ‎07-18-2020

Zynq Linear QSPI Flash stacked read fail on higher flash

I am using a Zynq 7030 device for my project. The module I am using comes with 2x Winbond 128Mbit QSPI flash devices. I have the HW platform configured to run the QSPI flash interface in Dual Quad SPI (4bit) mode in Vivado. The xparameters.h file of the generated BSP also has this line:

 

#define XPAR_PS7_QSPI_0_QSPI_MODE 1

 

 which means that the QSPI mode is XQSPIPS_CONNECTION_MODE_STACKED which is expected. 

I am running the xqspips_dual_flash_stack_lqspi_example.c example. The base test address is 0xFFF800 and a total of 16 pages (256bytes each) are being written and read in that test. This means that 8 pages are being written at the end of the lower flash and 8 pages are being written to the beginning of the higher flash. I am seeing that the writes are succeeding. However, when the linear QSPI read occurs, the 8 pages of the lower flash are being read correctly but the 8 pages of the upper flash are all being returned as 0. This means that the read is failing since if the write was failing, I would see 0xFF being returned since flash after erase is 0xFF and not 0. 

Another test I did that tells me that this might be a configuration issue is I used the "Program Flash" feature from Vitis to flash my custom application at offset 0x1000000 which is the base of the higher flash. I set the Flash type option in the Program Flash tool to qspi-x4-dual_stacked. The flash completed successfully and when I rebooted my board, the custom application loaded successfully. This tells me that my HW configuration is correct too.

I changed my FPGA configuration to use Dual Quad SPI Parallel (8 bit) and then loaded the xqspips_dual_flash_lqspi_example.c project. This one passed.

I am a bit lost as to why the Linear QSPI read is failing on the higher flash in the stacked configuration...

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abommera
Xilinx Employee
Xilinx Employee
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Registered: ‎10-12-2018

Hi @siddhantmodi ,

What is your schematic? whether it is designed for dual-stacked or dual parallel?

Please run the flash-polled example and share uart console log with us.

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/qspipsu/examples/xqspipsu_generic_flash_polled_example.c

You can modify TEST_ADDRESS of your higher flash and check.

/*
* Flash address to which data is to be written.
*/

#define TEST_ADDRESS 0x000000

It is working for me successfully.

QSPIPSU Generic Flash Polled Example Test
FlashID=0x20 0xBB 0x20
Flash connection mode : 1
where 0 - Single; 1 - Stacked; 2 - Parallel
FCTIndex: 19
ReadCmd: 0x6B, WriteCmd: 0x2, StatusCmd: 0x70, FSRFlag: 1
Successfully ran QSPIPSU Generic Flash Polled Example

 

Thanks & Regards
Anil B
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