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vishnu_kn
Visitor
Visitor
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Registered: ‎06-05-2018

Zynq PL IO state before while power-up

I'm working on Zynq XC7Z020CLG400.

Bank 34 is 3.3V, Bank 35 is 1.8V, Bank 13 not using, PS Bank are 3.3V.

Power Up sequence as follows 1V > 1.8V > 3.3V & 1.35V > PS_SRST_B

PUDC_B_34 pin is Tied to 3.3V using 10K resistor.

I can see 1.8V pulse in bank 35 and low voltage pulse in Bank 34 before Deasserting the PS_SRST_B.

Is it due to PUDC_B_34 tied to 3.3V? (ie. 3.3V is coming after 1.8V as per recommended power ON sequence, PUDC_B_34 is in Bank 34, IO voltage of Bank 34 is 3.3V.)

The waveform of 3.3V, PS_SRST_B, Bank 34 IO Pin, bank 35 IO pin is attached.

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denist
Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

It doesn't look like this is related to PUDC_B_34 but there's something wrong. Maybe with component on the board getting power before VCCO?

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