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Observer
Observer
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Registered: ‎01-19-2018

Zynq UltraScale+ Stuck in Reset When Booting From QSPI

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We developed a custom board with a Zynq UltraScale+, but much of the schematic is similar to the ZCU102 (just far fewer peripherals). While I was developing my application, I noticed no problems, I would develop, build and then program through a JTAG programmer (Platform Cable II). The last step was to create a boot image for QSPI flash, and boot off of that. The problem I'm noticing, is that when I switch to QSPI boot, nothing happens. And then when I connect a Digital MultiMeter between SRST_B and GND, the application kicks off. Naturally this makes me think that it's an electrical problem with SRST_B (there is a 4.7k ohm pullup on the board). I tried a few different configurations, (add 200k resistor to gnd, add 100k resistor to 1.8VDC) but no luck. The problem almost seems to need an "event" like a multimeter being connected.

My application is bare metal with 3 APUs running asymmetric code. I also have PMU FW and a FSBL (both Xilinx "default"). I feel pretty confident that the application is not the problem, because it runs perfectly fine once a multimeter is connected to SRST_B. Unless, there is a problem with the FSBL and reset. I am also programming a bitstream, which only has a Zynq MPSoC block and nothing else. Do I need a reset controller when there is nothing in PL? 

Has anyone had a similar problem before, or does this ring any bells? 

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Observer
Observer
147 Views
Registered: ‎01-19-2018

Re: Zynq UltraScale+ Stuck in Reset When Booting From QSPI

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We are not 100% through integration, so there is a chance that the issue is elsewhere - but I wanted to post this in case anyone came across this in the future.

I think the problem was that the PL I/O voltage banks were not set in accordance with the PCB. In Vivado, the PS I/O bank voltages were set, but since there was nothing in the block diagram (besides the Zynq Utlrascale+ block) we did not have a constraints file. This was oversight on our part, and was important because the I/O banks on the PL must default to 3.3V unless otherwise specified in the XDC file. On the PCB, one PL bank was 3.3V and the other was 1.8V - and since neither was declared in constraints I think this was messing up the 1.8V rail, which is the rail that powered the PS bank with the reset signals. 

We found this solution accidently, as we moved on in the project and added custom IP blocks that needed constraints the I/O bank was properly constrained.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: Zynq UltraScale+ Stuck in Reset When Booting From QSPI

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I would recommend to take oscilloscope shots of the power up (especially of PS_POR_B and PS_SRST_B) but there's a possibility that the capacitance of the probe with make the problem go away.

 

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Observer
Observer
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Registered: ‎01-19-2018

Re: Zynq UltraScale+ Stuck in Reset When Booting From QSPI

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We are not 100% through integration, so there is a chance that the issue is elsewhere - but I wanted to post this in case anyone came across this in the future.

I think the problem was that the PL I/O voltage banks were not set in accordance with the PCB. In Vivado, the PS I/O bank voltages were set, but since there was nothing in the block diagram (besides the Zynq Utlrascale+ block) we did not have a constraints file. This was oversight on our part, and was important because the I/O banks on the PL must default to 3.3V unless otherwise specified in the XDC file. On the PCB, one PL bank was 3.3V and the other was 1.8V - and since neither was declared in constraints I think this was messing up the 1.8V rail, which is the rail that powered the PS bank with the reset signals. 

We found this solution accidently, as we moved on in the project and added custom IP blocks that needed constraints the I/O bank was properly constrained.

View solution in original post

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