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824 Views
Registered: ‎04-27-2018

eMMC initalize failed in FSBL Stage

I have a eMMC initialization failure problem with my own zu19eg board.  The failure occurs at the FSBL Stage. I have been checked this problem following with the guide https://www.xilinx.com/support/answers/71019.html

The results are as attachmented. It is sure that IDCODE and PS_VERSION is appropriate and the eMMC model is in Xilinx supported list.

I have tried to boot the board with initramFS in Jtag mode. Anyway the system startup with emmc error. And the capacity of emmc is just 8KiB when i type the command "lsblk". Errors occur when i try to write or read the eMMC with typeing the command "dd if=/dev/zero of=/dev/mmcblk0 bs=512 count=10" or "dd if=/dev/mmcblk0 of=/dev/null bs=512 count=10". The errors are attached.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: eMMC initalize failed in FSBL Stage

Have you tried to slow down the interface following https://www.xilinx.com/support/answers/69368.html  ?

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740 Views
Registered: ‎04-27-2018

Re: eMMC initalize failed in FSBL Stage

Yes,i have tried.  But the problem still exists.

It always hangs at the below codes inside the funtion Xsdps_Change_BusWidth()  in  the file xsdps_options.c.

emmc_trap_in_normintr.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: eMMC initalize failed in FSBL Stage

What's the refernce clock for the controller setup in Vivado?

is it 200MHz?

The ROM runs the interface at 8MHz and it works consistently, right?

How much did you slow down the FSBL? 25MHz?

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711 Views
Registered: ‎04-27-2018

Re: eMMC initalize failed in FSBL Stage

Yes, the refernce clock for the controller setup in Vivado is 200MHZ and the bus width sets to 8bit. And i want to slow it down to 50MHZ.

I am sorry and not quite clear about the ROM runing the interface at 8MHZ.

However, i debug the fsbl and make sure it hangs at waiting for CMD6 transfer completed. It returns with timeout error.

All the emmc commands before CMD6 is well done. That is to say, it succeeds to intialize emmc card, change the clock frequency to 26MHZ which is for default speed and select the card, but it fails to change bus width. Changing the width is what CMD6 means to do.

PS: the card initialization flow as below figures show:

emmc_init_flow.pngcmd6_fail.png

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706 Views
Registered: ‎04-27-2018

Re: eMMC initalize failed in FSBL Stage

And i am confused because there is a confilicts between ug1085 and the codes in the fsbl. In ug1085, it says SD card sending CMD6 and eMMC sending ACMD6, but the codes does oppositely.

ug1085_change_bus_width_cmd6.pngfsbl_change_bus_width_cmd6.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-11-2011

Re: eMMC initalize failed in FSBL Stage

I forgot to ask the version of the tool used to generate the FSBL.

I didn't find any known issue with latest versions.

I doubt there's an issue with the code. I would focus more and board design, layout and signal integrity issues.

 

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Registered: ‎04-27-2018

Re: eMMC initalize failed in FSBL Stage

The fsbl code is generated by xsdk 2018.2. I agree with you and should focus more on board. 

Thank you.

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