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Observer
Observer
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Registered: ‎10-17-2012

zynq 7000: PS reconfigure PL at runtime?

I'm trying to reconfigurate PL after fsbl loaded bit. The procedures are:

1 .fsbl start,load bit and arm app code

2. Arm restart PL , follow the procedure in ug585:    

PL Initialization via PS Software
At any time, the devcfg.CTRL [PCFG_PROG_B] bit can be used to issue a global reset to the PL. If this 
bit is set Low, the PL begins its initialization process and the devcfg.STATUS [PCFG_INIT] bit is held 
Low until the [PCFG_PROG_B] bit is set High by the hardware. The programming sequence to 
initialize the PL include these steps:
1.Set [PCFG_PROG_B] signal to High
2.Set [PCFG_PROG_B] signal to Low
3.Poll the [PCFG_INIT] status for Reset
4.Set [PCFG_PROG_B] signal to High
5.Poll the [PCFG_INIT] status for Set

3. Then download bit into PL

Finally I read the register in PL, its same with the old ones.

So how to reconfiguration PL with new bit?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2013

Hi @oska874,

In step 3 you mentioned you download the bit file into the PL.

Can you provide more details on how you’ve done this?

Have you disabled the internal DevC loopback function as per UG585 v1.12.2, page 207 in section: PL Configuration via PS Software.

It would be great if you could provide more details on this so we can assist further.

 

Thanks,
Wendy
Xilinx Technical Support
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-21-2013

Hi @oska874

 

May I also ask is there a reason why you are following the procedure you are?

Can you provide more details on your runtime software?

We have drivers that look after the PL configuration via PS, so we may also be able advise you better once we have more information.

 

Thanks,
Wendy
Xilinx Technical Support
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Observer
Observer
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Registered: ‎10-17-2012

I download bit into PL with function "XDcfg_Transfer" of xdevcfg.c,provided by SDK.

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