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eestar
Participant
Participant
918 Views
Registered: ‎08-21-2012

zynq config failure by JTAG after download 100% stream

Hi,

I have a prolbem configuring fpga by JTAG, need help to give any idea? Maybe attached log can help for the analyzing.

my setup:
1) board is customer board design by ourself
2) using SDK 2015.2 to downlaod elf and bit file

image.png
my problem:
JTAG can see both arm and fpga, but after downloading the bitstream, will report failure.

98% 12MB 0.4MB/s 00:00 ETA
14:17:58 DEBUG : (XSDB Server)
100% 12MB 0.4MB/s 00:28
14:17:58 DEBUG : (XSDB Server)

14:17:58 DEBUG : XSDB Command: [fpga -file D:/Xilinx_workspace/euad_ezad_fpga_src-pa/ezad_mlk/ezad_pa_FreeRTOSv10.0.0/FreeRTOS-Plus/ezad/ezad_c1/ezad_c1_hw_platform/ezad_top_v2.bit], Result:[{Format=JTAG node is not accessible, Time=1567059478017, Code=1}, ]
14:17:58 ERROR : JTAG node is not accessible
14:17:58 ERROR : Exception occured while running Program FPGA.

in the log, we can get more status log such as:

XSDB Command: [fpga -config-status], Result:[null, CRC ERROR 0
DECRYPTOR ENABLE 0
PLL LOCK STATUS 1
DCI MATCH STATUS 1
END OF STARTUP (EOS) STATUS 0
GTS_CFG_B STATUS 0
GWE STATUS 0
GHIGH STATUS 0
MODE PIN M[0] 1
MODE PIN M[1] 1
MODE PIN M[2] 1
INIT_B INTERNAL SIGNAL STATUS 1
INIT_B PIN 1
DONE INTERNAL SIGNAL STATUS 0
DONE PIN 0
IDCODE ERROR 0
SECURITY ERROR 0
SYSTEM MONITOR OVER-TEMP ALARM STATUS 0
CFG STARTUP STATE MACHINE PHASE 0
RESERVED 0
CFG BUS WIDTH DETECTION 3
HMAC ERROR 0
PUDC_B PIN 1
BAD PACKET ERROR 0
CFGBVS PIN 1]

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3 Replies
drjohnsmith
Teacher
Teacher
901 Views
Registered: ‎07-09-2009

has this board and cable set worked before ?

    do you have more than one board, has this design worked before ?

 

This is your problem,

14:17:58 ERROR : JTAG node is not accessible
14:17:58 ERROR : Exception occured while running Program FPGA.
java.lang.RuntimeException: JTAG node is not accessible

Wondering what your JTAG path is, do you have buffers / switches that can be disabled by the FPGA / CPU

, does configuring the FPGA break the path ?

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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eestar
Participant
Participant
886 Views
Registered: ‎08-21-2012

Thanks for the qucik help!
This is a new build board, 2nd hardware version. Only one board.
We have an old version bitstream, it can program successfully, and DONE go high.
As my understanding, bitstream changing should not introdcue program problem, but in fact, new bitstream will trig the problem.
I just change some PS config, and PL pins. Of cource, internal logic also changed.

The bitstream has programed 100%, and not show CRC error, so my understanding is JTAG seems OK.
and from the log, "END OF STARTUP (EOS) STATUS" is low, After google, seems the internal fpga config state machine not started, don't know why.

Thanks &BR
Guoxing

 

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eestar
Participant
Participant
852 Views
Registered: ‎08-21-2012

the new bitstream contain 2 GTPs, after removing these 2 GTPs. Now we can program the fpga successfully.

I will continue investigating why GTPs will make programming fail.

 

BR

Guoxing

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