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Visitor
Visitor
5,570 Views
Registered: ‎12-08-2007

1/4 Rate DDS design technique

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Greetings,

 

I am trying to implement a decimated sine wave using a DDS in sysgen for a Virtex6. I am clocking the FPGA at 1/4 rate of the external DAC clock. (ie. FPGA=250MHz, DAC=1GHz). So for each FGPA clock (t) my 4 decimated sine wave outputs (n) need to be: t(0)=[n, n+1, n+2, n+3]; t(1)=[n+4, n+5, n+6, n+7]; etc.

 

Does anyone know of a clever technique for using a DDS to create a 1/4 rate decimated sine wave?

 

Thanks much,

Mike

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Visitor
Visitor
6,663 Views
Registered: ‎12-08-2007

Re: 1/4 Rate DDS design technique

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Thank much for the reply. I ended up just creating a ROM and using captured data from the DSP sine wave block and a homespun commutator in Simulink.

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Observer
Observer
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Registered: ‎05-16-2012

Re: 1/4 Rate DDS design technique

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This has recently been discussed in a german forum. Somebody wanted to create a 2GB DDS without the given chips, or instead needed a digital output.

 

It was somewhere here, but I could not find it at the moment.

http://www.mikrocontroller.net/forum/fpga-vhdl-cpld

 

Well in fact you need 4 parallel DDS units operating at their full speed. If you are also smoothing and filtering the waves, this will also have to be done in parallel then.

 

At that point of time I too searched for something like that but did fail.

 

I really regret too, that the known chips of AD like 9912 do not have a digital output, because then you might get this function with 2GHz speed for some $ only.

 

 

 

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Visitor
Visitor
6,664 Views
Registered: ‎12-08-2007

Re: 1/4 Rate DDS design technique

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Thank much for the reply. I ended up just creating a ROM and using captured data from the DSP sine wave block and a homespun commutator in Simulink.

View solution in original post

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Observer
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Registered: ‎05-16-2012

Re: 1/4 Rate DDS design technique

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How do you manage interpolation and / or filtering?

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Observer
Observer
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Registered: ‎05-16-2012

Re: 1/4 Rate DDS design technique

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nothing about that?

 

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