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wastie
Adventurer
Adventurer
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Registered: ‎02-12-2008

AIE Design with GBT and PCIe

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How would I design a system with PL, AIE, and PS? Where the data input is from a GBT and the output is to PCIe? The data is processed by the AIE and PL and possibly the PS as well? Can the IP blocks for the I/O feed data to Either the PS or the AIE/PL? This is for a VERSAL 1902.

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derekh
Xilinx Employee
Xilinx Employee
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Registered: ‎08-06-2018

This is a normal Communications scenario, so you will first need to analyze how you want to move data from transceivers to PCIe buffers and what kind of processing you will need in between.
Depending on how much interaction you want from PS side there are proposed approaches to the System Design covered in chapter 3 in this user guide.
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1273-versal-acap-design.pdf 

The nature of your signal processing also plays a role in which domain you should map your functions and accelerators.
Low latency, bit manipulations and tight timing controlled loops typically is done best in PL.
High throughput basic linear algebra and parallel computes typically maps to AI Engine.
Long term control, watchdogs and generic functions usually is for the PS application.

Sometimes you may also find it useful to put certain functions in non-optimal domain, because you need to save resources for other functions.
So yes, you can choose which domain you want to process the I/O feed, keep in mind that the feed need to fit the compute or data transportation capabilities for the different domains in that case.
If you choose to do e.g. a PS domain processing only, you are bound to the compute capability of the A72 and the memory bandwidths of the PS.

Also note that AI Engine should not be treated as the end station of your signal processing. It works by consuming input data (except for some cases of direct digital synthesis) and producing output data.
Decision making and analysis of the processed results is best placed in PL and PS depending on your response time requirements.

As the native data transportation between PL and AI Engine is AXIS Stream based, it fit naturally as signal processing accelerator. For some use cases, the data should be arranged in suitable batches to be processed, to allow for a continous usage of the AI Engine acceleration capabilities.

If you need further discussions regarding your specific system design, please coordinate with your local FAE.

Derek
SAE DSP and AI Engine, Xilinx Sweden/EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

HI @wastie 

I assume GBT means GigaBit Tranceivers right? (I usually use GT).

So when you have IOs to the output of the device, this needs to be defined in the platform. So you will not be able to use the VCK190 base platform.

Thus you need to create a Vivado Design for the vesal 1902 with PCIe and the GTs. Then you need to export the design to Vitis to generate the platform.

Some example you can be looking at:

One thing which is important to think about is how you are going to feed the AIE. This might be from the memory using either the GMIOs (see this tutorial for a reference) or the MM2S/S2MM IPs mentioned above. Or this might be a stream connection. I am not sure we have an example available publicly for this. But the way to do is to have AXI4-Stream unconnected in the vivado design with the AXI4-Stream interfaces enabled for the platform so vitis (v++) can connect the AIE to it.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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derekh
Xilinx Employee
Xilinx Employee
327 Views
Registered: ‎08-06-2018

This is a normal Communications scenario, so you will first need to analyze how you want to move data from transceivers to PCIe buffers and what kind of processing you will need in between.
Depending on how much interaction you want from PS side there are proposed approaches to the System Design covered in chapter 3 in this user guide.
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1273-versal-acap-design.pdf 

The nature of your signal processing also plays a role in which domain you should map your functions and accelerators.
Low latency, bit manipulations and tight timing controlled loops typically is done best in PL.
High throughput basic linear algebra and parallel computes typically maps to AI Engine.
Long term control, watchdogs and generic functions usually is for the PS application.

Sometimes you may also find it useful to put certain functions in non-optimal domain, because you need to save resources for other functions.
So yes, you can choose which domain you want to process the I/O feed, keep in mind that the feed need to fit the compute or data transportation capabilities for the different domains in that case.
If you choose to do e.g. a PS domain processing only, you are bound to the compute capability of the A72 and the memory bandwidths of the PS.

Also note that AI Engine should not be treated as the end station of your signal processing. It works by consuming input data (except for some cases of direct digital synthesis) and producing output data.
Decision making and analysis of the processed results is best placed in PL and PS depending on your response time requirements.

As the native data transportation between PL and AI Engine is AXIS Stream based, it fit naturally as signal processing accelerator. For some use cases, the data should be arranged in suitable batches to be processed, to allow for a continous usage of the AI Engine acceleration capabilities.

If you need further discussions regarding your specific system design, please coordinate with your local FAE.

Derek
SAE DSP and AI Engine, Xilinx Sweden/EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

florentw
Moderator
Moderator
233 Views
Registered: ‎11-09-2015

Hi @wastie 

Is everything clear for you on this topic? If yes, could you kindly mark a reply as acceped solution to close the thread?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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