03-07-2019 03:33 PM
I am trying to use DSP48E2 block to implement a 8 bit counter.
I came across Binary Counter V12.0 in the IP library. But it looks like the RTL and simulation is only available in VHDL.
I was wondering if this IP is available in verilog. I am more concerned with simulation aspect as I don't have mixed language simulator.
03-19-2019 05:22 AM
03-19-2019 08:35 AM
I am using ModelSim. I will switch to Vivado Simulator.
It is also possible to do mixed language simu using ModelSim. I suspect you have some Modelsim setting incorrect.
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.