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ami.kum
Adventurer
Adventurer
592 Views
Registered: ‎11-08-2018

Binary Counter v12.0 verilog file

Hi!

I am trying to use DSP48E2 block to implement a 8 bit counter. 

I came across Binary Counter V12.0 in the IP library. But it looks like the RTL and simulation is only available in VHDL. 

I was wondering if this IP is available in verilog. I am more concerned with simulation aspect as I don't have mixed language simulator. 

 

 

-AK

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4 Replies
vkanchan
Xilinx Employee
Xilinx Employee
534 Views
Registered: ‎09-18-2018

Hi @ami.kum 

The IP is only available in VHDL. Which simulator are you using ? If you have the Vivado simulator,it is a Mixed language simulator and it should work on it.

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ami.kum
Adventurer
Adventurer
518 Views
Registered: ‎11-08-2018

I am using ModelSim. I will switch to Vivado Simulator.

Thanks.

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dpaul24
Scholar
Scholar
512 Views
Registered: ‎08-07-2014

@ami.kum,

I am using ModelSim. I will switch to Vivado Simulator.

It is also possible to do mixed language simu using ModelSim. I suspect you have some Modelsim setting incorrect.

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ami.kum
Adventurer
Adventurer
507 Views
Registered: ‎11-08-2018

Yes. It requires a mixed language simulation license. I only have license version which support only Verilog.

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